From owner-freebsd-current Wed Apr 24 02:14:21 1996 Return-Path: owner-current Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id CAA01918 for current-outgoing; Wed, 24 Apr 1996 02:14:21 -0700 (PDT) Received: from GndRsh.aac.dev.com (GndRsh.aac.dev.com [198.145.92.241]) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id CAA01911 for ; Wed, 24 Apr 1996 02:14:16 -0700 (PDT) Received: (from rgrimes@localhost) by GndRsh.aac.dev.com (8.6.12/8.6.12) id CAA04144; Wed, 24 Apr 1996 02:12:52 -0700 From: "Rodney W. Grimes" Message-Id: <199604240912.CAA04144@GndRsh.aac.dev.com> Subject: Re: MotherBoard Jumper Settings... To: joerg_wunsch@uriah.heep.sax.de Date: Wed, 24 Apr 1996 02:12:52 -0700 (PDT) Cc: freebsd-current@FreeBSD.org, cat@ki.net, geoff@ki.net, scrappy@ki.net In-Reply-To: <199604240730.JAA26732@uriah.heep.sax.de> from J Wunsch at "Apr 24, 96 09:30:12 am" X-Mailer: ELM [version 2.4ME+ PL11 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-current@FreeBSD.org X-Loop: FreeBSD.org Precedence: bulk > As Marc G. Fournier wrote: > > > Third, the Oscillator Frequency was set for 33Mhz instead > > of 25Mhz...have fixed it... > > (Others told you that a DX4 is 3x, so the 33 MHz was right.) > > > As far as the cache is concerned, I have: > > > > 4x UM61512AK-15/95282/N52049's > > 1x W24129AK-15/95200 (Tag SRAM) > > > > Am I correct in assuming that the -15 is the speed of the cache? > > If so, and I haven't changed that one yet, my CMOS is set for 20ns... > > would that produce any of the bugs I've been reporting? > > I don't think so. The tag RAM is IMHO normally faster than the cache, > perhaps that's why they kept the cache timing slower than necessary in > the setup. This is only common when the data RAM is -20ns. The more ``usuall'' conditions are that the TAG is 15nS (though some times it can be safely 20nS) and the DATA is either 15 or 20nS. A few rare boards use 12nS parts for TAG and either 12 or 15nS parts for DATA. > > The jumpers for the cache are set for 256KB/64kbx4...how do I > > determine the size of each of the cache chips to determine if *this* is > > right? > > The 61512 suggests a 512 Kbit cache. Seems you are using only half of > it with your jumper setting. The 61512 is infact a 64k x 8 part, I looked it up as there had been too much speculation on here about just what that chip was. Cache RAM on 486 and later machines is almost always x 8 parts for those who thought this might have been a 128k x 4. Your cache jumper settings are correct at 256K/64Kx8. You may still have a bad cache RAM though. Do you ever get any signal 10's or 11's from the gcc compiler, or do you just get panics? -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD