Date: Tue, 28 Mar 2006 17:37:34 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 94183 for review Message-ID: <200603281737.k2SHbYVc050209@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=94183 Change 94183 by imp@imp_Speedy on 2006/03/28 17:37:03 Migrate from uart_{sg}etreg to WR4/RD4. We need to do this because the USART registers are 32 bits in size, not 8 bits. This shows up when we set certain bits in the interrupt register. Also, start down the path of using DMA for Rx and Tx. Affected files ... .. //depot/projects/arm/src/sys/arm/at91/uart_dev_at91usart.c#17 edit Differences ... ==== //depot/projects/arm/src/sys/arm/at91/uart_dev_at91usart.c#17 (text+ko) ==== @@ -41,11 +41,17 @@ #include <dev/uart/uart_bus.h> #include <arm/at91/at91rm92reg.h> #include <arm/at91/at91_usartreg.h> +#include <arm/at91/at91_pdcreg.h> #include "uart_if.h" #define DEFAULT_RCLK AT91C_MASTER_CLOCK +#define RD4(bas, reg) \ + bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) +#define WR4(bas, reg, value) \ + bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) + #define SIGCHG(c, i, s, d) \ do { \ if (c) { \ @@ -183,10 +189,13 @@ /* Turn on rx and tx */ cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX; - uart_setreg(bas, USART_CR, cr); - uart_setreg(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); - uart_setreg(bas, USART_IER, USART_CSR_TXRDY | USART_CSR_RXRDY | - USART_CSR_RXBRK); + WR4(bas, USART_CR, cr); + WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); + WR4(bas, USART_IER, USART_CSR_TIMEOUT | + USART_CSR_TXRDY | USART_CSR_RXRDY | + USART_CSR_RXBRK | USART_CSR_ENDRX | USART_CSR_ENDTX); + /* Set the receive timeout to be 1.5 character times. */ + WR4(bas, USART_RTOR, 12); } /* @@ -207,9 +216,9 @@ at91_usart_putc(struct uart_bas *bas, int c) { - while (!(uart_getreg(bas, USART_CSR) & + while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)); - uart_setreg(bas, USART_THR, c); + WR4(bas, USART_THR, c); } /* @@ -219,9 +228,9 @@ at91_usart_poll(struct uart_bas *bas) { - if (!(uart_getreg(bas, USART_CSR) & USART_CSR_RXRDY)) + if (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) return (-1); - return (uart_getreg(bas, USART_RHR) & 0xff); + return (RD4(bas, USART_RHR) & 0xff); } /* @@ -232,9 +241,9 @@ { int c; - while (!(uart_getreg(bas, USART_CSR) & USART_CSR_RXRDY)) + while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) ; - c = uart_getreg(bas, USART_RHR); + c = RD4(bas, USART_RHR); c &= 0xff; return (c); } @@ -302,7 +311,7 @@ * XXX: Gross hack : Skyeye doesn't raise an interrupt once the * transfer is done, so simulate it. */ - uart_setreg(&sc->sc_bas, USART_IER, USART_CSR_TXRDY); + WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY); #endif return (0); } @@ -322,7 +331,7 @@ } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); bas = &sc->sc_bas; mtx_lock_spin(&sc->sc_hwmtx); - cr = uart_getreg(bas, USART_CR); + cr = RD4(bas, USART_CR); cr &= ~(USART_CR_DTREN | USART_CR_DTRDIS | USART_CR_RTSEN | USART_CR_RTSDIS); if (new & SER_DTR) @@ -333,7 +342,7 @@ cr |= USART_CR_RTSEN; else cr |= USART_CR_RTSDIS; - uart_setreg(bas, USART_CR, cr); + WR4(bas, USART_CR, cr); mtx_unlock_spin(&sc->sc_hwmtx); return (0); } @@ -356,7 +365,7 @@ static int at91_usart_bus_ipend(struct uart_softc *sc) { - int csr = uart_getreg(&sc->sc_bas, USART_CSR); + int csr = RD4(&sc->sc_bas, USART_CSR); int ipend = 0; #ifdef USART0_CONSOLE @@ -371,13 +380,15 @@ mtx_lock_spin(&sc->sc_hwmtx); if (csr & USART_CSR_TXRDY && sc->sc_txbusy) ipend |= SER_INT_TXIDLE; - if (csr & USART_CSR_RXRDY) + if (csr & USART_CSR_ENDTX && sc->sc_txbusy) + ipend |= SER_INT_TXIDLE; + if (csr & (USART_CSR_RXRDY | USART_CSR_ENDRX | USART_CSR_TIMEOUT)) ipend |= SER_INT_RXREADY; if (csr & USART_CSR_RXBRK) { unsigned int cr = USART_CR_RSTSTA; ipend |= SER_INT_BREAK; - uart_setreg(&sc->sc_bas, USART_CR, cr); + WR4(&sc->sc_bas, USART_CR, cr); } mtx_unlock_spin(&sc->sc_hwmtx); return (ipend); @@ -395,7 +406,7 @@ uint8_t csr; mtx_lock_spin(&sc->sc_hwmtx); - csr = uart_getreg(&sc->sc_bas, USART_CSR); + csr = RD4(&sc->sc_bas, USART_CSR); sig = 0; if (csr & USART_CSR_CTS) sig |= SER_CTS;
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