From owner-svn-src-all@freebsd.org Fri Nov 8 19:03:36 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 51EB715BD4C; Fri, 8 Nov 2019 19:03:36 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 478qRr1Rbdz3HgJ; Fri, 8 Nov 2019 19:03:36 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 14E4029BA; Fri, 8 Nov 2019 19:03:36 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id xA8J3ZrF098060; Fri, 8 Nov 2019 19:03:35 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id xA8J3Ypt098054; Fri, 8 Nov 2019 19:03:34 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <201911081903.xA8J3Ypt098054@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Fri, 8 Nov 2019 19:03:34 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r354555 - head/sys/arm64/rockchip/clk X-SVN-Group: head X-SVN-Commit-Author: mmel X-SVN-Commit-Paths: head/sys/arm64/rockchip/clk X-SVN-Commit-Revision: 354555 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Nov 2019 19:03:36 -0000 Author: mmel Date: Fri Nov 8 19:03:34 2019 New Revision: 354555 URL: https://svnweb.freebsd.org/changeset/base/354555 Log: Cleanup Rockchip clocks implementation. - style - unify dprinf defines - make dprinf's 32-bit compatible Not a functional change. MFC after: 3 weeks Reviewed by: manu, imp Differential Revision: https://reviews.freebsd.org/D22281 Modified: head/sys/arm64/rockchip/clk/rk_clk_armclk.c head/sys/arm64/rockchip/clk/rk_clk_composite.c head/sys/arm64/rockchip/clk/rk_clk_gate.c head/sys/arm64/rockchip/clk/rk_clk_mux.c head/sys/arm64/rockchip/clk/rk_clk_pll.c head/sys/arm64/rockchip/clk/rk_cru.c Modified: head/sys/arm64/rockchip/clk/rk_clk_armclk.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_armclk.c Fri Nov 8 18:57:41 2019 (r354554) +++ head/sys/arm64/rockchip/clk/rk_clk_armclk.c Fri Nov 8 19:03:34 2019 (r354555) @@ -67,15 +67,19 @@ struct rk_clk_armclk_sc { CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) #define READ4(_clk, off, val) \ CLKDEV_READ_4(clknode_get_device(_clk), off, val) -#define DEVICE_LOCK(_clk) \ +#define DEVICE_LOCK(_clk) \ CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) #define DEVICE_UNLOCK(_clk) \ CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) #define RK_ARMCLK_WRITE_MASK_SHIFT 16 -/* #define dprintf(format, arg...) printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */ +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else #define dprintf(format, arg...) +#endif static int rk_clk_armclk_init(struct clknode *clk, device_t dev) @@ -132,7 +136,7 @@ rk_clk_armclk_recalc(struct clknode *clk, uint64_t *fr DEVICE_UNLOCK(clk); div = ((reg & sc->div_mask) >> sc->div_shift) + 1; - dprintf("parent_freq=%lu, div=%u\n", *freq, div); + dprintf("parent_freq=%ju, div=%u\n", *freq, div); *freq = *freq / div; @@ -152,7 +156,7 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t f sc = clknode_get_softc(clk); - dprintf("Finding best parent/div for target freq of %lu\n", *fout); + dprintf("Finding best parent/div for target freq of %ju\n", *fout); p_names = clknode_get_parent_names(clk); p_main = clknode_find_by_name(p_names[sc->main_parent]); @@ -162,7 +166,7 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t f div = sc->rates[i].div; best_p = best * div; rate = i; - dprintf("Best parent %s (%d) with best freq at %lu\n", + dprintf("Best parent %s (%d) with best freq at %ju\n", clknode_get_name(p_main), sc->main_parent, best); @@ -179,17 +183,18 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t f return (0); } - dprintf("Changing parent (%s) freq to %lu\n", clknode_get_name(p_main), best_p); + dprintf("Changing parent (%s) freq to %ju\n", clknode_get_name(p_main), + best_p); err = clknode_set_freq(p_main, best_p, 0, 1); if (err != 0) - printf("Cannot set %s to %lu\n", + printf("Cannot set %s to %ju\n", clknode_get_name(p_main), best_p); clknode_set_parent_by_idx(clk, sc->main_parent); clknode_get_freq(p_main, &best_p); - dprintf("main parent freq at %lu\n", best_p); + dprintf("main parent freq at %ju\n", best_p); DEVICE_LOCK(clk); val |= (div - 1) << sc->div_shift; val |= sc->div_mask << RK_ARMCLK_WRITE_MASK_SHIFT; Modified: head/sys/arm64/rockchip/clk/rk_clk_composite.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_composite.c Fri Nov 8 18:57:41 2019 (r354554) +++ head/sys/arm64/rockchip/clk/rk_clk_composite.c Fri Nov 8 19:03:34 2019 (r354555) @@ -61,15 +61,19 @@ struct rk_clk_composite_sc { CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) #define READ4(_clk, off, val) \ CLKDEV_READ_4(clknode_get_device(_clk), off, val) -#define DEVICE_LOCK(_clk) \ +#define DEVICE_LOCK(_clk) \ CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) #define DEVICE_UNLOCK(_clk) \ CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) #define RK_CLK_COMPOSITE_MASK_SHIFT 16 -/* #define dprintf(format, arg...) printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */ +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else #define dprintf(format, arg...) +#endif static int rk_clk_composite_init(struct clknode *clk, device_t dev) @@ -158,6 +162,7 @@ rk_clk_composite_recalc(struct clknode *clk, uint64_t dprintf("parent_freq=%lu, div=%u\n", *freq, div); *freq = *freq / div; + dprintf("Final freq=%ju\n", *freq); return (0); } @@ -194,20 +199,22 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_ sc = clknode_get_softc(clk); - dprintf("Finding best parent/div for target freq of %lu\n", *fout); + dprintf("Finding best parent/div for target freq of %ju\n", *fout); p_names = clknode_get_parent_names(clk); for (best_div = 0, best = 0, p_idx = 0; p_idx != clknode_get_parents_num(clk); p_idx++) { p_clk = clknode_find_by_name(p_names[p_idx]); clknode_get_freq(p_clk, &fparent); - dprintf("Testing with parent %s (%d) at freq %lu\n", clknode_get_name(p_clk), p_idx, fparent); + dprintf("Testing with parent %s (%d) at freq %ju\n", + clknode_get_name(p_clk), p_idx, fparent); div = rk_clk_composite_find_best(sc, fparent, *fout); cur = fparent / div; if ((*fout - cur) < (*fout - best)) { best = cur; best_div = div; best_parent = p_idx; - dprintf("Best parent so far %s (%d) with best freq at %lu\n", clknode_get_name(p_clk), p_idx, best); + dprintf("Best parent so far %s (%d) with best freq at " + "%ju\n", clknode_get_name(p_clk), p_idx, best); } } @@ -233,7 +240,8 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_ p_idx = clknode_get_parent_idx(clk); if (p_idx != best_parent) { - dprintf("Switching parent index from %d to %d\n", p_idx, best_parent); + dprintf("Switching parent index from %d to %d\n", p_idx, + best_parent); clknode_set_parent_by_idx(clk, best_parent); } @@ -266,7 +274,8 @@ DEFINE_CLASS_1(rk_clk_composite_clknode, rk_clk_compos clknode_class); int -rk_clk_composite_register(struct clkdom *clkdom, struct rk_clk_composite_def *clkdef) +rk_clk_composite_register(struct clkdom *clkdom, + struct rk_clk_composite_def *clkdef) { struct clknode *clk; struct rk_clk_composite_sc *sc; Modified: head/sys/arm64/rockchip/clk/rk_clk_gate.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_gate.c Fri Nov 8 18:57:41 2019 (r354554) +++ head/sys/arm64/rockchip/clk/rk_clk_gate.c Fri Nov 8 19:03:34 2019 (r354555) @@ -45,7 +45,7 @@ __FBSDID("$FreeBSD$"); CLKDEV_READ_4(clknode_get_device(_clk), off, val) #define MD4(_clk, off, clr, set ) \ CLKDEV_MODIFY_4(clknode_get_device(_clk), off, clr, set) -#define DEVICE_LOCK(_clk) \ +#define DEVICE_LOCK(_clk) \ CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) #define DEVICE_UNLOCK(_clk) \ CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) Modified: head/sys/arm64/rockchip/clk/rk_clk_mux.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_mux.c Fri Nov 8 18:57:41 2019 (r354554) +++ head/sys/arm64/rockchip/clk/rk_clk_mux.c Fri Nov 8 19:03:34 2019 (r354555) @@ -51,7 +51,7 @@ __FBSDID("$FreeBSD$"); CLKDEV_READ_4(clknode_get_device(_clk), off, val) #define MD4(_clk, off, clr, set ) \ CLKDEV_MODIFY_4(clknode_get_device(_clk), off, clr, set) -#define DEVICE_LOCK(_clk) \ +#define DEVICE_LOCK(_clk) \ CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) #define DEVICE_UNLOCK(_clk) \ CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.c Fri Nov 8 18:57:41 2019 (r354554) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.c Fri Nov 8 19:03:34 2019 (r354555) @@ -58,19 +58,23 @@ struct rk_clk_pll_sc { bool normal_mode; }; -#define WRITE4(_clk, off, val) \ +#define WRITE4(_clk, off, val) \ CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) -#define READ4(_clk, off, val) \ +#define READ4(_clk, off, val) \ CLKDEV_READ_4(clknode_get_device(_clk), off, val) -#define DEVICE_LOCK(_clk) \ +#define DEVICE_LOCK(_clk) \ CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) -#define DEVICE_UNLOCK(_clk) \ +#define DEVICE_UNLOCK(_clk) \ CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) #define RK_CLK_PLL_MASK_SHIFT 16 -/* #define dprintf(format, arg...) printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */ +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else #define dprintf(format, arg...) +#endif static int rk_clk_pll_set_gate(struct clknode *clk, bool enable) @@ -397,13 +401,18 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *f dprintf("con2: %x\n", con3); dprintf("con3: %x\n", con4); - fbdiv = (con1 & RK3399_CLK_PLL_FBDIV_MASK) >> RK3399_CLK_PLL_FBDIV_SHIFT; + fbdiv = (con1 & RK3399_CLK_PLL_FBDIV_MASK) + >> RK3399_CLK_PLL_FBDIV_SHIFT; - postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK) >> RK3399_CLK_PLL_POSTDIV1_SHIFT; - postdiv2 = (con2 & RK3399_CLK_PLL_POSTDIV2_MASK) >> RK3399_CLK_PLL_POSTDIV2_SHIFT; - refdiv = (con2 & RK3399_CLK_PLL_REFDIV_MASK) >> RK3399_CLK_PLL_REFDIV_SHIFT; + postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK) + >> RK3399_CLK_PLL_POSTDIV1_SHIFT; + postdiv2 = (con2 & RK3399_CLK_PLL_POSTDIV2_MASK) + >> RK3399_CLK_PLL_POSTDIV2_SHIFT; + refdiv = (con2 & RK3399_CLK_PLL_REFDIV_MASK) + >> RK3399_CLK_PLL_REFDIV_SHIFT; - fracdiv = (con3 & RK3399_CLK_PLL_FRAC_MASK) >> RK3399_CLK_PLL_FRAC_SHIFT; + fracdiv = (con3 & RK3399_CLK_PLL_FRAC_MASK) + >> RK3399_CLK_PLL_FRAC_SHIFT; fracdiv >>= 24; dsmpd = (con4 & RK3399_CLK_PLL_DSMPD_MASK) >> RK3399_CLK_PLL_DSMPD_SHIFT; @@ -415,7 +424,7 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *f dprintf("fracdiv: %d\n", fracdiv); dprintf("dsmpd: %d\n", dsmpd); - dprintf("parent freq=%lu\n", *freq); + dprintf("parent freq=%ju\n", *freq); if (dsmpd == 0) { /* Fractional mode */ @@ -424,10 +433,10 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *f /* Integer mode */ foutvco = *freq / refdiv * fbdiv; } - dprintf("foutvco: %lu\n", foutvco); + dprintf("foutvco: %ju\n", foutvco); *freq = foutvco / postdiv1 / postdiv2; - dprintf("freq: %lu\n", *freq); + dprintf("freq: %ju\n", *freq); return (0); } Modified: head/sys/arm64/rockchip/clk/rk_cru.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_cru.c Fri Nov 8 18:57:41 2019 (r354554) +++ head/sys/arm64/rockchip/clk/rk_cru.c Fri Nov 8 19:03:34 2019 (r354555) @@ -233,10 +233,12 @@ rk_cru_attach(device_t dev) case RK_CLK_UNDEFINED: break; case RK3328_CLK_PLL: - rk3328_clk_pll_register(sc->clkdom, sc->clks[i].clk.pll); + rk3328_clk_pll_register(sc->clkdom, + sc->clks[i].clk.pll); break; case RK3399_CLK_PLL: - rk3399_clk_pll_register(sc->clkdom, sc->clks[i].clk.pll); + rk3399_clk_pll_register(sc->clkdom, + sc->clks[i].clk.pll); break; case RK_CLK_COMPOSITE: rk_clk_composite_register(sc->clkdom, @@ -246,7 +248,8 @@ rk_cru_attach(device_t dev) rk_clk_mux_register(sc->clkdom, sc->clks[i].clk.mux); break; case RK_CLK_ARMCLK: - rk_clk_armclk_register(sc->clkdom, sc->clks[i].clk.armclk); + rk_clk_armclk_register(sc->clkdom, + sc->clks[i].clk.armclk); break; default: device_printf(dev, "Unknown clock type\n");