From nobody Wed Feb 11 20:44:01 2026 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4fB9QB0V01z6SBqX for ; Wed, 11 Feb 2026 20:44:02 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R13" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4fB9Q95ypcz3PKg for ; Wed, 11 Feb 2026 20:44:01 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1770842641; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=WQa50+52wPEB7n42FsJgpqwJa0YGfaJHrQmZFkP5HYk=; b=Ay8+cxY5xpCRfgfqYIYL8f6TJ1s1otAR5hHa3NoFg9KQOZMLaoKG3gTB0H6W/MAIlDzC6E xL51Na100jwTqLR+yMZG7uq0xhmfmJzcaPQSj3Vgrtv/jGe4HAaq2E1vmnPkxZF5zA4CPC sOG4qSogX8IQHocER99NtEeTAIB2GkbMnI6FKS85umOdv/FtxkIRsAraXnrFV+ZyEe+UX6 AZNTpFPBXy8kzcEbbtyrhVINZS+fuf99y8L3tmmEqaLbuc2yrJK6aUYdLt3Xzo77LSPRFR O3w0hR1O3LlTeOA5CsJqOC6Kf4IHtgDXCTwK976E03jtwT7EpzeakMnklP5gRw== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1770842641; a=rsa-sha256; cv=none; b=oMesJRqfxNQ2Awvaca/aEabwo7VSm5/h0nxDnG1wfDaOgQHo7ZDRKL3gefvw9vOzGEo15A HK9W2hR+b4iTGXHJ26/n7IJPUgJEcaguxSMBT0K01AaxAiGtvgXyI6POeXZN833LqdFfj0 r0ERZCHRBQwMUJX0/KRyN0Qn2sgM5aKLixYFZj4Zkxj6r//7auO7Yq/8N4K3/HEEzb6oe4 wibJQUcAHVn6p6yhAdkgO67oN9EXO7JGinyvBpaC8et0ULRRrX6cp5RzC3qx5wXOD9kiRY gMGJ8vSzKNg62ijqXHSvRNN+6tg0fxNapZLUKDxgxWfp/pQ7y3RJ4mWHfI/gGw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1770842641; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=WQa50+52wPEB7n42FsJgpqwJa0YGfaJHrQmZFkP5HYk=; b=LU4oSS4vhr3xje/mVqfiuV8qXyYnNVSNfzdd7+ntqobEtXq0CDFYAuHTGShBCdoigSoCq4 w/pT+gEAyxPv3ZuiXGklQP6tg+HAcfbgBZf3r47jXBZTFI/ZaLVGq254dAb7ifafkKtHMQ H9Z72SgacrBscYYkyGFjCOdD5jnWly8MXYi/J56MixX2D8sbjntbAtXHGj8tU2Z/lAKJ4y k0mHoFdvZy3gdpHQq/DLEr7YpoqO3R+KTbuID2UaLH2MriUgjDBgevopKh5pRBQgXbAPhd jOwUVKKAgOKusfM0w9FSNQsQV26QXTNk05o9rpSMTu+crIDT+JufQB6QSOfb5g== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4fB9Q95Tjrz153L for ; Wed, 11 Feb 2026 20:44:01 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 186bd by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Wed, 11 Feb 2026 20:44:01 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Olivier Certner Subject: git: df7b4dcdb8ff - main - hwpstate_amd(4): Sane defaults for min/max perf on insane capabilities List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: olce X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: df7b4dcdb8ff32a735916b50a473424b543c1e5e Auto-Submitted: auto-generated Date: Wed, 11 Feb 2026 20:44:01 +0000 Message-Id: <698cea11.186bd.4748259@gitrepo.freebsd.org> The branch main has been updated by olce: URL: https://cgit.FreeBSD.org/src/commit/?id=df7b4dcdb8ff32a735916b50a473424b543c1e5e commit df7b4dcdb8ff32a735916b50a473424b543c1e5e Author: Olivier Certner AuthorDate: 2026-01-29 21:14:48 +0000 Commit: Olivier Certner CommitDate: 2026-02-11 20:43:20 +0000 hwpstate_amd(4): Sane defaults for min/max perf on insane capabilities If the CPPC_CAPABILITY_1 register stays at its reset value (0) even after enabling CPPC, as observed in the field (see the referenced PR below), use sane min/max performance limits as hinted by the ACPI spec, i.e., all 0s for the minimum value and all 1s for the maximum one. While here, let's cope upfront with some more insane situations, where the minimum value would be greater than the maximum one, but also if they would be equal which does not seem to make sense at all in the CPPC frame (and, anyway, in this case, the actual minimum and maximum values we program should have no effect at all). That last case actually also covers the one exposed in the previous paragraph. PR: 292615 Reviewed by: aokblast Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D55007 --- sys/x86/cpufreq/hwpstate_amd.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c index d1186ae786ce..049699ea02d4 100644 --- a/sys/x86/cpufreq/hwpstate_amd.c +++ b/sys/x86/cpufreq/hwpstate_amd.c @@ -661,6 +661,7 @@ amd_set_autonomous_hwp_cb(void *args) { struct set_autonomous_hwp_data *const data = args; struct hwpstate_softc *const sc = data->sc; + uint64_t lowest_perf, highest_perf; int error; /* We proceed sequentially, so we'll clear out errors on progress. */ @@ -690,12 +691,30 @@ amd_set_autonomous_hwp_cb(void *args) * CPPC driver. */ SET_BITS_VALUE(sc->cppc.request, AMD_CPPC_REQUEST_EPP_BITS, 0x80); + + /* Enable autonomous mode by setting desired performance to 0. */ + SET_BITS_VALUE(sc->cppc.request, AMD_CPPC_REQUEST_DES_PERF_BITS, 0); + + /* + * When MSR_AMD_CPPC_CAPS_1 stays at its reset value (0) before CPPC + * activation (not supposed to happen, but happens in the field), we use + * reasonable default values that are explicitly described by the ACPI + * spec (all 0s for the minimum value, all 1s for the maximum one). + * Going further, we actually do the same as long as the minimum and + * maximum performance levels are not sorted or are equal (in which case + * CPPC is not supposed to make sense at all), which covers the reset + * value case. + */ + lowest_perf = BITS_VALUE(AMD_CPPC_CAPS_1_LOWEST_PERF_BITS, data->caps); + highest_perf = BITS_VALUE(AMD_CPPC_CAPS_1_HIGHEST_PERF_BITS, data->caps); + if (lowest_perf >= highest_perf) { + lowest_perf = 0; + highest_perf = -1; + } SET_BITS_VALUE(sc->cppc.request, AMD_CPPC_REQUEST_MIN_PERF_BITS, - BITS_VALUE(AMD_CPPC_CAPS_1_LOWEST_PERF_BITS, data->caps)); + lowest_perf); SET_BITS_VALUE(sc->cppc.request, AMD_CPPC_REQUEST_MAX_PERF_BITS, - BITS_VALUE(AMD_CPPC_CAPS_1_HIGHEST_PERF_BITS, data->caps)); - /* enable autonomous mode by setting desired performance to 0 */ - SET_BITS_VALUE(sc->cppc.request, AMD_CPPC_REQUEST_DES_PERF_BITS, 0); + highest_perf); error = wrmsr_safe(MSR_AMD_CPPC_REQUEST, sc->cppc.request); if (error != 0)