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From: Marius Strobl <marius@FreeBSD.org>
Date: Sat, 16 Apr 2005 15:05:56 +0000 (UTC)
To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org,
	cvs-all@FreeBSD.org
X-FreeBSD-CVS-Branch: HEAD
Subject: cvs commit: src/sys/sparc64/sparc64 exception.S genassym.c
 interrupt.S intr_machdep.c
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marius      2005-04-16 15:05:56 UTC

  FreeBSD src repository

  Modified files:
    sys/sparc64/sparc64  exception.S genassym.c interrupt.S 
                         intr_machdep.c 
  Log:
  - MFi386: sys/i386/i386/intr_machdep.c rev. 1.11
    Don't use atomic ops to increment interrupt stats.
    On sparc64 this reduces delay until tick interrupts are service by 1/10th
    on average. In turn this reduces the clock drift caused by these delays
    so there's less drift which has to be compensated in tick_hardclock().
    This includes switching from atomically incrementing the global cnt.v_intr
    to the asm equivalent of PCPU_LAZY_INC(cnt.v_intr) in exception.S
  - Correct some comments to match the registers actually used.
  - Correct some format specifiers, interrupt levels passed in are u_int.
  - Use FBSDID.
  
  Ok'ed by:       jhb
  
  Revision  Changes    Path
  1.70      +15 -11    src/sys/sparc64/sparc64/exception.S
  1.57      +4 -1      src/sys/sparc64/sparc64/genassym.c
  1.8       +8 -7      src/sys/sparc64/sparc64/interrupt.S
  1.23      +1 -1      src/sys/sparc64/sparc64/intr_machdep.c