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Date: Mon, 9 Dec 2013 13:14:39 +0100
Message-ID: <CAFHCsPUkFOfSJFRn0vsC+pQu0zE+vu4u96K-68g8eqQ4QJbM8g@mail.gmail.com>
Subject: _bus_dmamap_sync() and L2 cache sync
From: Svatopluk Kraus <onwahe@gmail.com>
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Hi,

when I and Michal Meloun were debugging problems on our ethernet driver on
arm11 mpcore platform at work, we found out that rx/tx descriptors rings
are not correctly synced for DMA. These descriptors are mapped as
uncachable, i.e. their bus_dmamap_t maps have DMAMAP_COHERENT flag set.

We realized that L2 cache must be synced the same way as L1 cache. I.e., L2
cache write buffer and others must be flushed before DMA is started.

Now, in our implementation, we always call cache_dma_sync() in the
beginning of _bus_dmamap_sync() even for DMAMAP_COHERENT maps. The
cache_dma_sync() is implemented as:

static __inline void
cache_dma_sync(void)
{

    dsb();
    l2cache.sync(l2cache.arg);
    dsb();
}

Regards,
Svatopluk Kraus