From owner-svn-src-head@FreeBSD.ORG Mon Nov 8 19:15:32 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 4D045106566B; Mon, 8 Nov 2010 19:15:32 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 20D278FC14; Mon, 8 Nov 2010 19:15:32 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oA8JFWaj047579; Mon, 8 Nov 2010 19:15:32 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oA8JFWPj047577; Mon, 8 Nov 2010 19:15:32 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201011081915.oA8JFWPj047577@svn.freebsd.org> From: Pyun YongHyeon Date: Mon, 8 Nov 2010 19:15:32 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r214992 - head/sys/dev/re X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Nov 2010 19:15:32 -0000 Author: yongari Date: Mon Nov 8 19:15:31 2010 New Revision: 214992 URL: http://svn.freebsd.org/changeset/base/214992 Log: Reduce spin wait time consumed in GMII register access routine. There were a couple of attempts in the past to reduce it since it took more than 1ms. Because mii_tick() periodically polls link status, waiting more than 1ms for each GMII register access was overkill. Unfortunately all previous attempts were failed with various ways on different controllers. This time, add additional 20us dealy at the end of GMII register access which seems to requirement of all RealTek controllers to issue next GMII register access request. This is the same way what Linux does. Modified: head/sys/dev/re/if_re.c Modified: head/sys/dev/re/if_re.c ============================================================================== --- head/sys/dev/re/if_re.c Mon Nov 8 19:12:19 2010 (r214991) +++ head/sys/dev/re/if_re.c Mon Nov 8 19:15:31 2010 (r214992) @@ -423,13 +423,12 @@ re_gmii_readreg(device_t dev, int phy, i } CSR_WRITE_4(sc, RL_PHYAR, reg << 16); - DELAY(1000); for (i = 0; i < RL_PHY_TIMEOUT; i++) { rval = CSR_READ_4(sc, RL_PHYAR); if (rval & RL_PHYAR_BUSY) break; - DELAY(100); + DELAY(25); } if (i == RL_PHY_TIMEOUT) { @@ -437,6 +436,11 @@ re_gmii_readreg(device_t dev, int phy, i return (0); } + /* + * Controller requires a 20us delay to process next MDIO request. + */ + DELAY(20); + return (rval & RL_PHYAR_PHYDATA); } @@ -451,13 +455,12 @@ re_gmii_writereg(device_t dev, int phy, CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); - DELAY(1000); for (i = 0; i < RL_PHY_TIMEOUT; i++) { rval = CSR_READ_4(sc, RL_PHYAR); if (!(rval & RL_PHYAR_BUSY)) break; - DELAY(100); + DELAY(25); } if (i == RL_PHY_TIMEOUT) { @@ -465,6 +468,11 @@ re_gmii_writereg(device_t dev, int phy, return (0); } + /* + * Controller requires a 20us delay to process next MDIO request. + */ + DELAY(20); + return (0); }