From owner-freebsd-current@FreeBSD.ORG Tue Jul 3 01:08:41 2007 Return-Path: X-Original-To: current@freebsd.org Delivered-To: freebsd-current@FreeBSD.ORG Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 9914C16A400 for ; Tue, 3 Jul 2007 01:08:41 +0000 (UTC) (envelope-from ssouhlal@FreeBSD.org) Received: from elvis.mu.org (elvis.mu.org [192.203.228.196]) by mx1.freebsd.org (Postfix) with ESMTP id 8611613C4E3 for ; Tue, 3 Jul 2007 01:08:41 +0000 (UTC) (envelope-from ssouhlal@FreeBSD.org) Received: from [192.168.0.97] (c-76-21-32-5.hsd1.ca.comcast.net [76.21.32.5]) by elvis.mu.org (Postfix) with ESMTP id 4D54E1A3C1A; Mon, 2 Jul 2007 18:08:41 -0700 (PDT) In-Reply-To: <3bbf2fe10707021518l3d4257d6o3b8838faa6d1ace5@mail.gmail.com> References: <20070701224452.I552@10.0.0.1> <20070701224741.M552@10.0.0.1> <3bbf2fe10707021518l3d4257d6o3b8838faa6d1ace5@mail.gmail.com> Mime-Version: 1.0 (Apple Message framework v752.3) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: Content-Transfer-Encoding: 7bit From: Suleiman Souhlal Date: Mon, 2 Jul 2007 18:08:32 -0700 To: Attilio Rao X-Mailer: Apple Mail (2.752.3) Cc: Jeff Roberson , current@freebsd.org Subject: Re: New SCHED_SMP diff. X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Jul 2007 01:08:41 -0000 On Jul 2, 2007, at 3:18 PM, Attilio Rao wrote: > 2007/7/2, Jeff Roberson : >> I forgot: >> >> http://people.freebsd.org/~jeff/schedsmp.diff >> >> --- amd64/amd64/cpu_switch.S 6 Jun 2007 07:35:07 -0000 1.158 >> +++ amd64/amd64/cpu_switch.S 2 Jul 2007 05:43:31 -0000 >> @@ -148,13 +148,7 @@ >> movq %cr3,%rax >> cmpq %rcx,%rax /* Same address space? */ >> jne swinact >> - movq %rdx, TD_LOCK(%rdi) /* Release the old thread */ >> - /* Wait for the new thread to become unblocked */ >> - movq $blocked_lock, %rdx >> -1: >> - movq TD_LOCK(%rsi),%rcx >> - cmpq %rcx, %rdx >> - je 1b >> + xchgq %rdx, TD_LOCK(%rdi) /* Release the old thread */ > > I don't think here you need an atomic instruction, a memory barrier > throug sfence is good enough in order to make thread migration > consistent. SFENCE is not needed. Stores are already strongly ordered wrt other stores on x86 (unless you use write-combining memory or non-temporal stores). The main advantage of using an atomic operation when unlocking is that it should make the store visible to other CPUs faster (so they don't spin as long), although I think you'll have a hard time noticing a difference in a macrobenchmark. -- Suleiman