Date: Mon, 12 Jun 2023 17:56:38 GMT From: Mark Johnston <markj@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 266b0663c598 - main - =?utf-8?Q?qat:=20Add=20Intel=C2=AE=204xxx=20Series=20VF=20driver=20support?= Message-ID: <202306121756.35CHuchT092939@gitrepo.freebsd.org>
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The branch main has been updated by markj: URL: https://cgit.FreeBSD.org/src/commit/?id=266b0663c598b7e50c2998974c16f89b7ac23e3a commit 266b0663c598b7e50c2998974c16f89b7ac23e3a Author: Krzysztof Zdziarski <krzysztofx.zdziarski@intel.com> AuthorDate: 2023-06-12 17:10:03 +0000 Commit: Mark Johnston <markj@FreeBSD.org> CommitDate: 2023-06-12 17:44:01 +0000 qat: Add Intel® 4xxx Series VF driver support Overview: Intel(R) QuickAssist Technology (Intel(R) QAT) provides hardware acceleration for offloading security, authentication and compression services from the CPU, thus significantly increasing the performance and efficiency of standard platform solutions. This commit introduces: - Intel® 4xxx Series VF driver support. - Device configurability via sysctls. - UIO support for Intel® 4xxx Series devices. Patch co-authored by: Krzysztof Zdziarski <krzysztofx.zdziarski@intel.com> Patch co-authored by: Michal Gulbicki <michalx.gulbicki@intel.com> Patch co-authored by: Julian Grajkowski <julianx.grajkowski@intel.com> Patch co-authored by: Piotr Kasierski <piotrx.kasierski@intel.com> Patch co-authored by: Lukasz Kolodzinski <lukaszx.kolodzinski@intel.com> Patch co-authored by: Karol Grzadziel <karolx.grzadziel@intel.com> Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D39850 --- share/man/man4/qat.4 | 57 +- sys/contrib/dev/qat/qat_4xxx.bin | Bin 532308 -> 665356 bytes sys/dev/qat/include/adf_cfg_device.h | 24 +- sys/dev/qat/include/adf_gen2_pfvf.h | 27 + sys/dev/qat/include/adf_gen4_pfvf.h | 16 + sys/dev/qat/include/adf_gen4_timer.h | 17 + sys/dev/qat/include/adf_gen4vf_hw_csr_data.h | 151 + sys/dev/qat/include/adf_pf2vf_msg.h | 182 - sys/dev/qat/include/adf_pfvf_vf_msg.h | 13 + sys/dev/qat/include/common/adf_accel_devices.h | 86 +- sys/dev/qat/include/common/adf_cfg.h | 5 + sys/dev/qat/include/common/adf_cfg_common.h | 21 +- sys/dev/qat/include/common/adf_cfg_strings.h | 6 + sys/dev/qat/include/common/adf_cfg_sysctl.h | 12 + sys/dev/qat/include/common/adf_common_drv.h | 75 +- sys/dev/qat/include/common/adf_gen2_hw_data.h | 24 + sys/dev/qat/include/common/adf_gen4_hw_data.h | 41 + sys/dev/qat/include/common/adf_pfvf_msg.h | 260 + sys/dev/qat/include/common/adf_pfvf_utils.h | 44 + sys/dev/qat/include/common/adf_pfvf_vf_proto.h | 32 + sys/dev/qat/include/common/adf_uio.h | 17 + sys/dev/qat/include/common/adf_uio_cleanup.h | 11 + sys/dev/qat/include/common/adf_uio_control.h | 43 + sys/dev/qat/qat/qat_ocf.c | 198 +- .../qat/qat_api/common/compression/dc_buffers.c | 16 + sys/dev/qat/qat_api/common/compression/dc_chain.c | 102 + .../qat/qat_api/common/compression/dc_datapath.c | 6 + sys/dev/qat/qat_api/common/compression/dc_dp.c | 8 + .../qat_api/common/compression/dc_ns_datapath.c | 72 + .../common/compression/dc_ns_header_footer.c | 46 + .../qat/qat_api/common/compression/dc_session.c | 27 +- .../common/compression/include/dc_session.h | 2 - .../qat_api/common/crypto/sym/key/lac_sym_key.c | 8 - .../qat_api/common/crypto/sym/lac_sym_alg_chain.c | 4 +- sys/dev/qat/qat_api/common/ctrl/sal_compression.c | 63 +- .../qat/qat_api/common/ctrl/sal_ctrl_services.c | 101 +- .../qat/qat_api/common/ctrl/sal_get_instances.c | 288 + .../qat_api/common/include/sal_types_compression.h | 5 +- sys/dev/qat/qat_api/common/stubs/lac_stubs.c | 191 + .../qat/qat_api/firmware/include/icp_qat_fw_mmp.h | 7808 ++++++++++++-------- .../qat_api/firmware/include/icp_qat_fw_mmp_ids.h | 508 +- sys/dev/qat/qat_api/include/cpa.h | 128 +- sys/dev/qat/qat_api/include/cpa_dev.h | 2 +- sys/dev/qat/qat_api/include/cpa_types.h | 21 +- sys/dev/qat/qat_api/include/dc/cpa_dc.h | 1008 ++- sys/dev/qat/qat_api/include/dc/cpa_dc_bp.h | 2 +- sys/dev/qat/qat_api/include/dc/cpa_dc_chain.h | 659 ++ sys/dev/qat/qat_api/include/dc/cpa_dc_dp.h | 97 +- sys/dev/qat/qat_api/include/icp_sal_versions.h | 2 +- sys/dev/qat/qat_api/include/lac/cpa_cy_common.h | 39 +- sys/dev/qat/qat_api/include/lac/cpa_cy_dh.h | 8 +- sys/dev/qat/qat_api/include/lac/cpa_cy_dsa.h | 2 +- sys/dev/qat/qat_api/include/lac/cpa_cy_ec.h | 454 +- sys/dev/qat/qat_api/include/lac/cpa_cy_ecdh.h | 3 +- sys/dev/qat/qat_api/include/lac/cpa_cy_ecdsa.h | 19 +- sys/dev/qat/qat_api/include/lac/cpa_cy_ecsm2.h | 1464 ++++ sys/dev/qat/qat_api/include/lac/cpa_cy_im.h | 5 +- sys/dev/qat/qat_api/include/lac/cpa_cy_key.h | 9 +- sys/dev/qat/qat_api/include/lac/cpa_cy_kpt.h | 853 +++ sys/dev/qat/qat_api/include/lac/cpa_cy_ln.h | 20 +- sys/dev/qat/qat_api/include/lac/cpa_cy_prime.h | 2 +- sys/dev/qat/qat_api/include/lac/cpa_cy_rsa.h | 18 +- sys/dev/qat/qat_api/include/lac/cpa_cy_sym.h | 17 +- sys/dev/qat/qat_api/include/lac/cpa_cy_sym_dp.h | 2 +- .../qat_api/qat_direct/include/icp_accel_devices.h | 5 +- sys/dev/qat/qat_common/adf_aer.c | 2 - sys/dev/qat/qat_common/adf_cfg.c | 49 + sys/dev/qat/qat_common/adf_cfg_device.c | 566 +- sys/dev/qat/qat_common/adf_cfg_sysctl.c | 343 + sys/dev/qat/qat_common/adf_ctl_drv.c | 491 ++ sys/dev/qat/qat_common/adf_freebsd_dev_processes.c | 677 ++ sys/dev/qat/qat_common/adf_freebsd_uio.c | 450 ++ sys/dev/qat/qat_common/adf_freebsd_uio_cleanup.c | 404 + sys/dev/qat/qat_common/adf_gen2_hw_data.c | 18 +- sys/dev/qat/qat_common/adf_gen4_hw_data.c | 85 +- sys/dev/qat/qat_common/adf_gen4_pfvf.c | 131 + sys/dev/qat/qat_common/adf_gen4_timer.c | 134 + sys/dev/qat/qat_common/adf_gen4vf_hw_csr_data.c | 162 + sys/dev/qat/qat_common/adf_hw_arbiter.c | 26 +- sys/dev/qat/qat_common/adf_init.c | 46 +- sys/dev/qat/qat_common/adf_pf2vf_capabilities.c | 147 - sys/dev/qat/qat_common/adf_pf2vf_msg.c | 896 --- sys/dev/qat/qat_common/adf_pf2vf_ring_to_svc_map.c | 74 - sys/dev/qat/qat_common/adf_pfvf_utils.c | 102 + sys/dev/qat/qat_common/adf_pfvf_vf_msg.c | 185 + sys/dev/qat/qat_common/adf_pfvf_vf_proto.c | 405 + sys/dev/qat/qat_common/adf_transport.c | 14 +- sys/dev/qat/qat_common/adf_vf2pf_msg.c | 275 - sys/dev/qat/qat_common/adf_vf_isr.c | 344 +- sys/dev/qat/qat_common/qat_common_module.c | 5 +- sys/dev/qat/qat_hw/qat_200xx/adf_200xx_hw_data.c | 21 +- sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c | 93 +- sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h | 6 +- sys/dev/qat/qat_hw/qat_4xxx/adf_drv.c | 10 +- sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c | 390 + sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h | 34 + sys/dev/qat/qat_hw/qat_4xxxvf/adf_drv.c | 282 + sys/dev/qat/qat_hw/qat_c3xxx/adf_c3xxx_hw_data.c | 21 +- sys/dev/qat/qat_hw/qat_c4xxx/adf_c4xxx_hw_data.c | 21 +- sys/dev/qat/qat_hw/qat_c62x/adf_c62x_hw_data.c | 21 +- .../qat/qat_hw/qat_dh895xcc/adf_dh895xcc_hw_data.c | 21 +- sys/modules/qat/qat_api/Makefile | 4 + sys/modules/qat/qat_common/Makefile | 14 +- sys/modules/qat/qat_hw/Makefile | 1 + 104 files changed, 16620 insertions(+), 5806 deletions(-) diff --git a/share/man/man4/qat.4 b/share/man/man4/qat.4 index e8a46a99e949..77b85d729ffa 100644 --- a/share/man/man4/qat.4 +++ b/share/man/man4/qat.4 @@ -1,7 +1,7 @@ .\" SPDX-License-Identifier: BSD-3-Clause .\" Copyright(c) 2007-2022 Intel Corporation .\" $FreeBSD$ -.Dd September 1, 2022 +.Dd May 4, 2023 .Dt QAT 4 .Os .Sh NAME @@ -101,6 +101,61 @@ For details of usage and supported operations and algorithms refer to the documentation mentioned above and .Sx SEE ALSO section. +.Sh SYSCTL_VARIABLES +Following variables may be used to reconfigure the QAT device.\& +For configuration persistence those variables may be set before loading the driver, either via +.Xr kenv 1 +or +.Xr loader.conf(5). +The device specific configuration options are prefixed with +.Va dev.qat.X\&. +where X is the device number. +The specific device needs to be in "down" state before changing the configuration. +.Bl -tag -width indent +.It Va state +Show current state of the device. Override the device state. Possible values: "down", "up". + +NOTE: If the symmetric services are used for device the qat_ocf driver needs to be disabled prior the device +reconfiguration. +Following variable may be used to enable/disable the QAT cryptographic framework connectivity +.Va dev.qat_ocf.0.enable\&. +Enabled by default. +.It Va cfg_services +Override the device services enabled: symmetric, asymmetric, data compression. +Possible values: "sym", "asym", "dc", "sym;dc", "asym;dc", "sym;asym". +Default services configured are "sym;asym" for even and "dc" for odd devices. +.It Va cfg_mode +Override the device mode configuration for kernel space and user space instances. +Possible values: "ks", "us", "ks;us". +Default value "ks;us". +.It Va num_user_processes +Override the number of uio user space processes that can connect to the QAT device. +Default: 2 +.El +.Pp +The following +.Xr sysctl 8 +variables are read-only: +.Bl -tag -width indent +.It Va frequency +QAT device frequency value. +.It Va mmp_version +QAT MMP Library revision number. +.It Va hw_version +QAT hardware revision number. +.It Va fw_version +QAT firmware revision number. +.It Va dev_cfg +Summary of device specific configuration. +.It Va heartbeat +QAT device heartbeat status. Value '1' indicates that the device is operational. +'0' value means that the device is not responsive. Device requires restart. +.It Va heartbeat_failed +Number of QAT heartbeat failures received. +.It Va heartbeat_sent +Number of QAT heartbeat requests sent. +.El + .Sh COMPATIBILITY The .Nm diff --git a/sys/contrib/dev/qat/qat_4xxx.bin b/sys/contrib/dev/qat/qat_4xxx.bin index baec3ad9ca32..66dd803fe419 100644 Binary files a/sys/contrib/dev/qat/qat_4xxx.bin and b/sys/contrib/dev/qat/qat_4xxx.bin differ diff --git a/sys/dev/qat/include/adf_cfg_device.h b/sys/dev/qat/include/adf_cfg_device.h index 9def937cc9db..267905dd0c4f 100644 --- a/sys/dev/qat/include/adf_cfg_device.h +++ b/sys/dev/qat/include/adf_cfg_device.h @@ -13,14 +13,14 @@ #define ADF_CFG_STATIC_CONF_DC_INTER_BUF_SIZE 64 #define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_ENABLED 1 #define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_DC 1 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_DH 0 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_DRBG 0 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_DSA 0 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_ECC 0 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_KEYGEN 0 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_LN 0 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_PRIME 0 -#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_RSA 0 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_DH 1 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_DRBG 1 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_DSA 1 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_ECC 1 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_KEYGEN 1 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_LN 1 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_PRIME 1 +#define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_RSA 1 #define ADF_CFG_STATIC_CONF_SAL_STATS_CFG_SYM 1 #define ADF_CFG_STATIC_CONF_POLL 1 #define ADF_CFG_STATIC_CONF_IRQ 0 @@ -30,6 +30,14 @@ #define ADF_CFG_STATIC_CONF_INST_NUM_DC 2 #define ADF_CFG_STATIC_CONF_INST_NUM_CY_POLL 6 #define ADF_CFG_STATIC_CONF_INST_NUM_CY_IRQ 2 +#define ADF_CFG_STATIC_CONF_USER_PROCESSES_NUM 2 +#define ADF_CFG_STATIC_CONF_USER_INST_NUM_CY 6 +#define ADF_CFG_STATIC_CONF_USER_INST_NUM_DC 2 +#define ADF_CFG_STATIC_CONF_INST_NUM_CY_POLL_VF 1 +#define ADF_CFG_STATIC_CONF_INST_NUM_CY_IRQ_VF 1 +#define ADF_CFG_STATIC_CONF_INST_NUM_DC_VF 2 +#define ADF_CFG_STATIC_CONF_USER_INST_NUM_CY_VF 2 +#define ADF_CFG_STATIC_CONF_USER_INST_NUM_DC_VF 2 #define ADF_CFG_FW_STRING_TO_ID(str, acc, id) \ do { \ diff --git a/sys/dev/qat/include/adf_gen2_pfvf.h b/sys/dev/qat/include/adf_gen2_pfvf.h new file mode 100644 index 000000000000..f5c565a9679b --- /dev/null +++ b/sys/dev/qat/include/adf_gen2_pfvf.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright(c) 2007-2022 Intel Corporation */ +/* $FreeBSD$ */ +#ifndef ADF_GEN2_PFVF_H +#define ADF_GEN2_PFVF_H + +#include <linux/types.h> +#include "adf_accel_devices.h" + +#define ADF_GEN2_ERRSOU3 (0x3A000 + 0x0C) +#define ADF_GEN2_ERRSOU5 (0x3A000 + 0xD8) +#define ADF_GEN2_ERRMSK3 (0x3A000 + 0x1C) +#define ADF_GEN2_ERRMSK5 (0x3A000 + 0xDC) + +static inline void +adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) +{ + pfvf_ops->enable_comms = adf_pfvf_comms_disabled; +} + +static inline void +adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) +{ + pfvf_ops->enable_comms = adf_pfvf_comms_disabled; +} + +#endif /* ADF_GEN2_PFVF_H */ diff --git a/sys/dev/qat/include/adf_gen4_pfvf.h b/sys/dev/qat/include/adf_gen4_pfvf.h new file mode 100644 index 000000000000..45fa171ae364 --- /dev/null +++ b/sys/dev/qat/include/adf_gen4_pfvf.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright(c) 2007-2022 Intel Corporation */ +/* $FreeBSD$ */ +#ifndef ADF_GEN4_PFVF_H +#define ADF_GEN4_PFVF_H + +#include "adf_accel_devices.h" + +void adf_gen4_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops); +static inline void +adf_gen4_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) +{ + pfvf_ops->enable_comms = adf_pfvf_comms_disabled; +} + +#endif /* ADF_GEN4_PFVF_H */ diff --git a/sys/dev/qat/include/adf_gen4_timer.h b/sys/dev/qat/include/adf_gen4_timer.h new file mode 100644 index 000000000000..e91591772e5e --- /dev/null +++ b/sys/dev/qat/include/adf_gen4_timer.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright(c) 2007-2022 Intel Corporation */ +/* $FreeBSD$ */ +#ifndef ADF_GEN4_TIMER_H_ +#define ADF_GEN4_TIMER_H_ + +struct adf_accel_dev; + +struct adf_hb_timer_data { + struct adf_accel_dev *accel_dev; + struct work_struct hb_int_timer_work; +}; + +int adf_int_timer_init(struct adf_accel_dev *accel_dev); +void adf_int_timer_exit(struct adf_accel_dev *accel_dev); + +#endif /* ADF_GEN4_TIMER_H_ */ diff --git a/sys/dev/qat/include/adf_gen4vf_hw_csr_data.h b/sys/dev/qat/include/adf_gen4vf_hw_csr_data.h new file mode 100644 index 000000000000..27f10ae729db --- /dev/null +++ b/sys/dev/qat/include/adf_gen4vf_hw_csr_data.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright(c) 2007-2022 Intel Corporation */ +/* $FreeBSD$ */ +#ifndef ADF_GEN4VF_HW_CSR_DATA_H_ +#define ADF_GEN4VF_HW_CSR_DATA_H_ + +#define ADF_RING_CSR_ADDR_OFFSET_GEN4VF 0x0 +#define ADF_RING_BUNDLE_SIZE_GEN4 0x2000 +#define ADF_RING_CSR_RING_HEAD 0x0C0 +#define ADF_RING_CSR_RING_TAIL 0x100 +#define ADF_RING_CSR_E_STAT 0x14C +#define ADF_RING_CSR_RING_CONFIG_GEN4 0x1000 +#define ADF_RING_CSR_RING_LBASE_GEN4 0x1040 +#define ADF_RING_CSR_RING_UBASE_GEN4 0x1080 +#define ADF_RING_CSR_INT_FLAG 0x170 +#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 +#define ADF_RING_CSR_NEXT_INT_SRCSEL 0x4 +#define ADF_RING_CSR_INT_SRCSEL 0x174 +#define ADF_RING_CSR_INT_COL_EN 0x17C +#define ADF_RING_CSR_INT_COL_CTL 0x180 +#define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C +#define ADF_BANK_INT_SRC_SEL_MASK_GEN4 0x44UL +#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 +#define ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4 0x3 +#define ADF_RINGS_PER_INT_SRCSEL_GEN4 2 + +#define BUILD_RING_BASE_ADDR_GEN4(addr, size) \ + ((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6) +#define READ_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_RING_HEAD + ((ring) << 2)) +#define READ_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_RING_TAIL + ((ring) << 2)) +#define READ_CSR_E_STAT_GEN4VF(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_E_STAT) +#define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_RING_CONFIG_GEN4 + ((ring) << 2), \ + (value)) +#define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \ + do { \ + struct resource *_csr_base_addr = csr_base_addr; \ + u32 _bank = bank; \ + u32 _ring = ring; \ + dma_addr_t _value = value; \ + u32 l_base = 0, u_base = 0; \ + l_base = (u32)((_value)&0xFFFFFFFF); \ + u_base = (u32)(((_value)&0xFFFFFFFF00000000ULL) >> 32); \ + ADF_CSR_WR((_csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (_bank)) + \ + ADF_RING_CSR_RING_LBASE_GEN4 + ((_ring) << 2), \ + l_base); \ + ADF_CSR_WR((_csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (_bank)) + \ + ADF_RING_CSR_RING_UBASE_GEN4 + ((_ring) << 2), \ + u_base); \ + } while (0) + +static inline u64 +read_base_gen4vf(struct resource *csr_base_addr, u32 bank, u32 ring) +{ + u32 l_base, u_base; + u64 addr; + + l_base = ADF_CSR_RD(csr_base_addr, + (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + + ADF_RING_CSR_RING_LBASE_GEN4 + (ring << 2)); + u_base = ADF_CSR_RD(csr_base_addr, + (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + + ADF_RING_CSR_RING_UBASE_GEN4 + (ring << 2)); + + addr = (u64)l_base & 0x00000000FFFFFFFFULL; + addr |= (u64)u_base << 32 & 0xFFFFFFFF00000000ULL; + + return addr; +} + +#define WRITE_CSR_INT_SRCSEL_GEN4VF(csr_base_addr, bank) \ + ADF_CSR_WR((csr_base_addr), \ + ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank) + \ + ADF_RING_CSR_INT_SRCSEL, \ + ADF_BANK_INT_SRC_SEL_MASK_GEN4) + +#define READ_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring) \ + read_base_gen4vf((csr_base_addr), (bank), (ring)) + +#define WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_RING_HEAD + ((ring) << 2), \ + (value)) +#define WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_RING_TAIL + ((ring) << 2), \ + (value)) +#define WRITE_CSR_INT_FLAG_GEN4VF(csr_base_addr, bank, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_INT_FLAG, \ + (value)) +#define WRITE_CSR_INT_COL_EN_GEN4VF(csr_base_addr, bank, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_INT_COL_EN, \ + (value)) +#define WRITE_CSR_INT_COL_CTL_GEN4VF(csr_base_addr, bank, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_INT_COL_CTL, \ + (value)) +#define WRITE_CSR_INT_FLAG_AND_COL_GEN4VF(csr_base_addr, bank, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_INT_FLAG_AND_COL, \ + (value)) +#define READ_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_RING_SRV_ARB_EN) +#define WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value) \ + ADF_CSR_WR((csr_base_addr), \ + (ADF_RING_CSR_ADDR_OFFSET_GEN4VF + \ + ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ + ADF_RING_CSR_RING_SRV_ARB_EN, \ + (value)) + +struct adf_hw_csr_info; +void gen4vf_init_hw_csr_info(struct adf_hw_csr_info *csr_info); + +#endif /* ADF_GEN4VF_HW_CSR_DATA_H_ */ diff --git a/sys/dev/qat/include/adf_pf2vf_msg.h b/sys/dev/qat/include/adf_pf2vf_msg.h deleted file mode 100644 index 9c8462a8f6b6..000000000000 --- a/sys/dev/qat/include/adf_pf2vf_msg.h +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright(c) 2007-2022 Intel Corporation */ -/* $FreeBSD$ */ -#ifndef ADF_PF2VF_MSG_H -#define ADF_PF2VF_MSG_H - -/* - * PF<->VF Messaging - * The PF has an array of 32-bit PF2VF registers, one for each VF. The - * PF can access all these registers; each VF can access only the one - * register associated with that particular VF. - * - * The register functionally is split into two parts: - * The bottom half is for PF->VF messages. In particular when the first - * bit of this register (bit 0) gets set an interrupt will be triggered - * in the respective VF. - * The top half is for VF->PF messages. In particular when the first bit - * of this half of register (bit 16) gets set an interrupt will be triggered - * in the PF. - * - * The remaining bits within this register are available to encode messages. - * and implement a collision control mechanism to prevent concurrent use of - * the PF2VF register by both the PF and VF. - * - * 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - * _______________________________________________ - * | | | | | | | | | | | | | | | | | - * +-----------------------------------------------+ - * \___________________________/ \_________/ ^ ^ - * ^ ^ | | - * | | | VF2PF Int - * | | Message Origin - * | Message Type - * Message-specific Data/Reserved - * - * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - * _______________________________________________ - * | | | | | | | | | | | | | | | | | - * +-----------------------------------------------+ - * \___________________________/ \_________/ ^ ^ - * ^ ^ | | - * | | | PF2VF Int - * | | Message Origin - * | Message Type - * Message-specific Data/Reserved - * - * Message Origin (Should always be 1) - * A legacy out-of-tree QAT driver allowed for a set of messages not supported - * by this driver; these had a Msg Origin of 0 and are ignored by this driver. - * - * When a PF or VF attempts to send a message in the lower or upper 16 bits, - * respectively, the other 16 bits are written to first with a defined - * IN_USE_BY pattern as part of a collision control scheme (see adf_iov_putmsg). - */ - -/* VF/PF compatibility version. */ -/* ADF_PFVF_COMPATIBILITY_EXT_CAP: Support for extended capabilities */ -#define ADF_PFVF_COMPATIBILITY_CAPABILITIES 2 -/* ADF_PFVF_COMPATIBILITY_FAST_ACK: In-use pattern cleared by receiver */ -#define ADF_PFVF_COMPATIBILITY_FAST_ACK 3 -#define ADF_PFVF_COMPATIBILITY_RING_TO_SVC_MAP 4 -#define ADF_PFVF_COMPATIBILITY_VERSION 4 /* PF<->VF compat */ - -/* PF->VF messages */ -#define ADF_PF2VF_INT BIT(0) -#define ADF_PF2VF_MSGORIGIN_SYSTEM BIT(1) -#define ADF_PF2VF_MSGTYPE_MASK 0x0000003C -#define ADF_PF2VF_MSGTYPE_SHIFT 2 -#define ADF_PF2VF_MSGTYPE_RESTARTING 0x01 -#define ADF_PF2VF_MSGTYPE_VERSION_RESP 0x02 -#define ADF_PF2VF_MSGTYPE_BLOCK_RESP 0x03 -#define ADF_PF2VF_MSGTYPE_FATAL_ERROR 0x04 -#define ADF_PF2VF_IN_USE_BY_PF 0x6AC20000 -#define ADF_PF2VF_IN_USE_BY_PF_MASK 0xFFFE0000 - -/* PF->VF Version Response */ -#define ADF_PF2VF_VERSION_RESP_VERS_MASK 0x00003FC0 -#define ADF_PF2VF_VERSION_RESP_VERS_SHIFT 6 -#define ADF_PF2VF_VERSION_RESP_RESULT_MASK 0x0000C000 -#define ADF_PF2VF_VERSION_RESP_RESULT_SHIFT 14 -#define ADF_PF2VF_MINORVERSION_SHIFT 6 -#define ADF_PF2VF_MAJORVERSION_SHIFT 10 -#define ADF_PF2VF_VF_COMPATIBLE 1 -#define ADF_PF2VF_VF_INCOMPATIBLE 2 -#define ADF_PF2VF_VF_COMPAT_UNKNOWN 3 - -/* PF->VF Block Request Type */ -#define ADF_VF2PF_MIN_SMALL_MESSAGE_TYPE 0 -#define ADF_VF2PF_MAX_SMALL_MESSAGE_TYPE (ADF_VF2PF_MIN_SMALL_MESSAGE_TYPE + 15) -#define ADF_VF2PF_MIN_MEDIUM_MESSAGE_TYPE (ADF_VF2PF_MAX_SMALL_MESSAGE_TYPE + 1) -#define ADF_VF2PF_MAX_MEDIUM_MESSAGE_TYPE \ - (ADF_VF2PF_MIN_MEDIUM_MESSAGE_TYPE + 7) -#define ADF_VF2PF_MIN_LARGE_MESSAGE_TYPE (ADF_VF2PF_MAX_MEDIUM_MESSAGE_TYPE + 1) -#define ADF_VF2PF_MAX_LARGE_MESSAGE_TYPE (ADF_VF2PF_MIN_LARGE_MESSAGE_TYPE + 3) -#define ADF_VF2PF_SMALL_PAYLOAD_SIZE 30 -#define ADF_VF2PF_MEDIUM_PAYLOAD_SIZE 62 -#define ADF_VF2PF_LARGE_PAYLOAD_SIZE 126 - -#define ADF_VF2PF_MAX_BLOCK_TYPE 3 -#define ADF_VF2PF_BLOCK_REQ_TYPE_SHIFT 22 -#define ADF_VF2PF_LARGE_BLOCK_BYTE_NUM_SHIFT 24 -#define ADF_VF2PF_MEDIUM_BLOCK_BYTE_NUM_SHIFT 25 -#define ADF_VF2PF_SMALL_BLOCK_BYTE_NUM_SHIFT 26 -#define ADF_VF2PF_BLOCK_REQ_CRC_SHIFT 31 -#define ADF_VF2PF_LARGE_BLOCK_BYTE_NUM_MASK 0x7F000000 -#define ADF_VF2PF_MEDIUM_BLOCK_BYTE_NUM_MASK 0x7E000000 -#define ADF_VF2PF_SMALL_BLOCK_BYTE_NUM_MASK 0x7C000000 -#define ADF_VF2PF_LARGE_BLOCK_REQ_TYPE_MASK 0xC00000 -#define ADF_VF2PF_MEDIUM_BLOCK_REQ_TYPE_MASK 0x1C00000 -#define ADF_VF2PF_SMALL_BLOCK_REQ_TYPE_MASK 0x3C00000 - -/* PF->VF Block Response Type */ -#define ADF_PF2VF_BLOCK_RESP_TYPE_DATA 0x0 -#define ADF_PF2VF_BLOCK_RESP_TYPE_CRC 0x1 -#define ADF_PF2VF_BLOCK_RESP_TYPE_ERROR 0x2 -#define ADF_PF2VF_BLOCK_RESP_TYPE_SHIFT 6 -#define ADF_PF2VF_BLOCK_RESP_DATA_SHIFT 8 -#define ADF_PF2VF_BLOCK_RESP_TYPE_MASK 0x000000C0 -#define ADF_PF2VF_BLOCK_RESP_DATA_MASK 0x0000FF00 - -/* PF-VF block message header bytes */ -#define ADF_VF2PF_BLOCK_VERSION_BYTE 0 -#define ADF_VF2PF_BLOCK_LEN_BYTE 1 -#define ADF_VF2PF_BLOCK_DATA 2 - -/* PF->VF Block Error Code */ -#define ADF_PF2VF_INVALID_BLOCK_TYPE 0x0 -#define ADF_PF2VF_INVALID_BYTE_NUM_REQ 0x1 -#define ADF_PF2VF_PAYLOAD_TRUNCATED 0x2 -#define ADF_PF2VF_UNSPECIFIED_ERROR 0x3 - -/* VF->PF messages */ -#define ADF_VF2PF_IN_USE_BY_VF 0x00006AC2 -#define ADF_VF2PF_IN_USE_BY_VF_MASK 0x0000FFFE -#define ADF_VF2PF_INT BIT(16) -#define ADF_VF2PF_MSGORIGIN_SYSTEM BIT(17) -#define ADF_VF2PF_MSGTYPE_MASK 0x003C0000 -#define ADF_VF2PF_MSGTYPE_SHIFT 18 -#define ADF_VF2PF_MSGTYPE_INIT 0x3 -#define ADF_VF2PF_MSGTYPE_SHUTDOWN 0x4 -#define ADF_VF2PF_MSGTYPE_VERSION_REQ 0x5 -#define ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ 0x6 -#define ADF_VF2PF_MSGTYPE_GET_LARGE_BLOCK_REQ 0x7 -#define ADF_VF2PF_MSGTYPE_GET_MEDIUM_BLOCK_REQ 0x8 -#define ADF_VF2PF_MSGTYPE_GET_SMALL_BLOCK_REQ 0x9 -#define ADF_VF2PF_MSGTYPE_NOTIFY 0xa -#define ADF_VF2PF_MSGGENC_RESTARTING_COMPLETE 0x0 - -/* Block message types - * 0..15 - 32 byte message - * 16..23 - 64 byte message - * 24..27 - 128 byte message - * 2 - Get Capability Request message - */ -#define ADF_VF2PF_BLOCK_MSG_CAP_SUMMARY 2 -#define ADF_VF2PF_BLOCK_MSG_GET_RING_TO_SVC_REQ 0x3 - -/* VF->PF Compatible Version Request */ -#define ADF_VF2PF_COMPAT_VER_REQ_SHIFT 22 - -/* How long to wait for far side to acknowledge receipt */ -#define ADF_IOV_MSG_ACK_DELAY_US 5 -#define ADF_IOV_MSG_ACK_EXP_MAX_DELAY_US (5 * 1000) -#define ADF_IOV_MSG_ACK_DELAY_MS 5 -#define ADF_IOV_MSG_ACK_LIN_MAX_DELAY_US (2 * 1000 * 1000) -/* If CSR is busy, how long to delay before retrying */ -#define ADF_IOV_MSG_RETRY_DELAY 5 -#define ADF_IOV_MSG_MAX_RETRIES 10 -/* How long to wait for a response from the other side */ -#define ADF_IOV_MSG_RESP_TIMEOUT 100 -/* How often to retry when there is no response */ -#define ADF_IOV_MSG_RESP_RETRIES 5 - -#define ADF_IOV_RATELIMIT_INTERVAL 8 -#define ADF_IOV_RATELIMIT_BURST 130 - -/* CRC Calculation */ -#define ADF_CRC8_INIT_VALUE 0xFF -/* PF VF message byte shift */ -#define ADF_PFVF_DATA_SHIFT 8 -#define ADF_PFVF_DATA_MASK 0xFF -#endif /* ADF_IOV_MSG_H */ diff --git a/sys/dev/qat/include/adf_pfvf_vf_msg.h b/sys/dev/qat/include/adf_pfvf_vf_msg.h new file mode 100644 index 000000000000..89ed5a740b29 --- /dev/null +++ b/sys/dev/qat/include/adf_pfvf_vf_msg.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright(c) 2007-2022 Intel Corporation */ +/* $FreeBSD$ */ +#ifndef ADF_PFVF_VF_MSG_H +#define ADF_PFVF_VF_MSG_H + +int adf_vf2pf_notify_init(struct adf_accel_dev *accel_dev); +void adf_vf2pf_notify_shutdown(struct adf_accel_dev *accel_dev); +int adf_vf2pf_request_version(struct adf_accel_dev *accel_dev); +int adf_vf2pf_get_capabilities(struct adf_accel_dev *accel_dev); +int adf_vf2pf_get_ring_to_svc(struct adf_accel_dev *accel_dev); + +#endif /* ADF_PFVF_VF_MSG_H */ diff --git a/sys/dev/qat/include/common/adf_accel_devices.h b/sys/dev/qat/include/common/adf_accel_devices.h index 9503069ac2a2..225b86a2a7e1 100644 --- a/sys/dev/qat/include/common/adf_accel_devices.h +++ b/sys/dev/qat/include/common/adf_accel_devices.h @@ -6,6 +6,7 @@ #include "qat_freebsd.h" #include "adf_cfg_common.h" +#include "adf_pfvf_msg.h" #define ADF_CFG_NUM_SERVICES 4 @@ -20,6 +21,7 @@ #define ADF_C4XXX_DEVICE_NAME "c4xxx" #define ADF_C4XXXVF_DEVICE_NAME "c4xxxvf" #define ADF_4XXX_DEVICE_NAME "4xxx" +#define ADF_4XXXVF_DEVICE_NAME "4xxxvf" #define ADF_DH895XCC_PCI_DEVICE_ID 0x435 #define ADF_DH895XCCIOV_PCI_DEVICE_ID 0x443 #define ADF_C62X_PCI_DEVICE_ID 0x37c8 @@ -33,13 +35,17 @@ #define ADF_C4XXX_PCI_DEVICE_ID 0x18a0 #define ADF_C4XXXIOV_PCI_DEVICE_ID 0x18a1 #define ADF_4XXX_PCI_DEVICE_ID 0x4940 +#define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941 #define ADF_401XX_PCI_DEVICE_ID 0x4942 +#define ADF_401XXIOV_PCI_DEVICE_ID 0x4943 #define IS_QAT_GEN3(ID) ({ (ID == ADF_C4XXX_PCI_DEVICE_ID); }) static inline bool IS_QAT_GEN4(const unsigned int id) { - return (id == ADF_4XXX_PCI_DEVICE_ID || id == ADF_401XX_PCI_DEVICE_ID); + return (id == ADF_4XXX_PCI_DEVICE_ID || id == ADF_401XX_PCI_DEVICE_ID || + id == ADF_4XXXIOV_PCI_DEVICE_ID || + id == ADF_401XXIOV_PCI_DEVICE_ID); } #define IS_QAT_GEN3_OR_GEN4(ID) (IS_QAT_GEN3(ID) || IS_QAT_GEN4(ID)) @@ -85,7 +91,7 @@ IS_QAT_GEN4(const unsigned int id) (((ena_srv_mask) >> (ADF_SRV_TYPE_BIT_LEN * (srv))) & ADF_SRV_TYPE_MASK) #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.csr_ops) - +#define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.pfvf_ops) #define ADF_DEFAULT_RING_TO_SRV_MAP \ (CRYPTO | CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \ NA << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \ @@ -266,6 +272,9 @@ struct adf_hw_csr_ops { u32 bank, u32 ring, u32 value); + bus_addr_t (*read_csr_ring_base)(struct resource *csr_base_addr, + u32 bank, + u32 ring); void (*write_csr_ring_base)(struct resource *csr_base_addr, u32 bank, u32 ring, @@ -288,10 +297,36 @@ struct adf_hw_csr_ops { void (*write_csr_ring_srv_arb_en)(struct resource *csr_base_addr, u32 bank, u32 value); + u32 (*get_src_sel_mask)(void); + u32 (*get_int_col_ctl_enable_mask)(void); + u32 (*get_bank_irq_mask)(u32 irq_mask); +}; + +struct adf_cfg_device_data; +struct adf_accel_dev; +struct adf_etr_data; +struct adf_etr_ring_data; + +struct adf_pfvf_ops { + int (*enable_comms)(struct adf_accel_dev *accel_dev); + u32 (*get_pf2vf_offset)(u32 i); + u32 (*get_vf2pf_offset)(u32 i); + void (*enable_vf2pf_interrupts)(struct resource *pmisc_addr, + u32 vf_mask); + void (*disable_all_vf2pf_interrupts)(struct resource *pmisc_addr); + u32 (*disable_pending_vf2pf_interrupts)(struct resource *pmisc_addr); + int (*send_msg)(struct adf_accel_dev *accel_dev, + struct pfvf_message msg, + u32 pfvf_offset, + struct mutex *csr_lock); + struct pfvf_message (*recv_msg)(struct adf_accel_dev *accel_dev, + u32 pfvf_offset, + u8 compat_ver); }; struct adf_hw_csr_info { struct adf_hw_csr_ops csr_ops; + struct adf_pfvf_ops pfvf_ops; u32 csr_addr_offset; u32 ring_bundle_size; u32 bank_int_flag_clear_mask; @@ -299,11 +334,6 @@ struct adf_hw_csr_info { u32 arb_enable_mask; }; -struct adf_cfg_device_data; -struct adf_accel_dev; -struct adf_etr_data; -struct adf_etr_ring_data; - struct adf_hw_device_data { struct adf_hw_device_class *dev_class; uint32_t (*get_accel_mask)(struct adf_accel_dev *accel_dev); @@ -315,9 +345,6 @@ struct adf_hw_device_data { uint32_t (*get_num_accels)(struct adf_hw_device_data *self); void (*notify_and_wait_ethernet)(struct adf_accel_dev *accel_dev); bool (*get_eth_doorbell_msg)(struct adf_accel_dev *accel_dev); - uint32_t (*get_pf2vf_offset)(uint32_t i); - uint32_t (*get_vintmsk_offset)(uint32_t i); - u32 (*get_vintsou_offset)(void); void (*get_arb_info)(struct arb_info *arb_csrs_info); void (*get_admin_info)(struct admin_info *admin_csrs_info); void (*get_errsou_offset)(u32 *errsou3, u32 *errsou5); @@ -352,6 +379,8 @@ struct adf_hw_device_data { const uint32_t **cfg); int (*init_device)(struct adf_accel_dev *accel_dev); int (*get_heartbeat_status)(struct adf_accel_dev *accel_dev); + int (*int_timer_init)(struct adf_accel_dev *accel_dev); + void (*int_timer_exit)(struct adf_accel_dev *accel_dev); uint32_t (*get_ae_clock)(struct adf_hw_device_data *self); uint32_t (*get_hb_clock)(struct adf_hw_device_data *self); void (*disable_iov)(struct adf_accel_dev *accel_dev); @@ -360,8 +389,10 @@ struct adf_hw_device_data { void (*enable_ints)(struct adf_accel_dev *accel_dev); bool (*check_slice_hang)(struct adf_accel_dev *accel_dev); int (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev); - int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev); - int (*disable_vf2pf_comms)(struct adf_accel_dev *accel_dev); + void (*enable_pf2vf_interrupt)(struct adf_accel_dev *accel_dev); + void (*disable_pf2vf_interrupt)(struct adf_accel_dev *accel_dev); + int (*interrupt_active_pf2vf)(struct adf_accel_dev *accel_dev); + int (*get_int_active_bundles)(struct adf_accel_dev *accel_dev); void (*reset_device)(struct adf_accel_dev *accel_dev); void (*reset_hw_units)(struct adf_accel_dev *accel_dev); int (*measure_clock)(struct adf_accel_dev *accel_dev); @@ -378,6 +409,11 @@ struct adf_hw_device_data { char *aeidstr); void (*remove_misc_error)(struct adf_accel_dev *accel_dev); int (*configure_accel_units)(struct adf_accel_dev *accel_dev); + int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, + u32 bank_number); + void (*config_ring_irq)(struct adf_accel_dev *accel_dev, + u32 bank_number, + u16 ring_mask); uint32_t (*get_objs_num)(struct adf_accel_dev *accel_dev); const char *(*get_obj_name)(struct adf_accel_dev *accel_dev, enum adf_accel_unit_services services); @@ -411,7 +447,6 @@ struct adf_hw_device_data { uint8_t num_accel; uint8_t num_logical_accel; uint8_t num_engines; - uint8_t min_iov_compat_ver; int (*get_storage_enabled)(struct adf_accel_dev *accel_dev, uint32_t *storage_enabled); u8 query_storage_cap; @@ -419,6 +454,7 @@ struct adf_hw_device_data { u8 storage_enable; u32 extended_dc_capabilities; int (*config_device)(struct adf_accel_dev *accel_dev); + u32 asym_ae_active_thd_mask; u16 asym_rings_mask; int (*get_fw_image_type)(struct adf_accel_dev *accel_dev, enum adf_cfg_fw_image_type *fw_image_type); @@ -603,6 +639,15 @@ struct adf_fw_versions { u8 mmp_version_patch; }; +struct adf_int_timer { + struct adf_accel_dev *accel_dev; + struct workqueue_struct *timer_irq_wq; + struct timer_list timer; + u32 timeout_val; + u32 int_cnt; + bool enabled; +}; + #define ADF_COMPAT_CHECKER_MAX 8 typedef int (*adf_iov_compat_checker_t)(struct adf_accel_dev *accel_dev, u8 vf_compat_ver); @@ -620,7 +665,9 @@ struct adf_accel_dev { struct adf_cfg_device_data *cfg; struct adf_fw_loader_data *fw_loader; struct adf_admin_comms *admin; + struct adf_uio_control_accel *accel; struct adf_heartbeat *heartbeat; + struct adf_int_timer *int_timer; struct adf_fw_versions fw_versions; unsigned int autoreset_on_error; struct adf_fw_counters_data *fw_counters_data; @@ -648,17 +695,18 @@ struct adf_accel_dev { int num_vfs; } pf; struct { + bool irq_enabled; struct resource *irq; void *cookie; - char *irq_name; struct task pf2vf_bh_tasklet; struct mutex vf2pf_lock; /* protect CSR access */ - int iov_msg_completion; - uint8_t compatible; - uint8_t pf_version; - u8 pf2vf_block_byte; - u8 pf2vf_block_resp_type; + struct completion msg_received; + struct pfvf_message + response; /* temp field holding pf2vf response */ + enum ring_reset_result rpreset_sts; + struct mutex rpreset_lock; /* protect rpreset_sts */ struct pfvf_stats pfvf_counters; + u8 pf_compat_ver; } vf; } u1; bool is_vf; diff --git a/sys/dev/qat/include/common/adf_cfg.h b/sys/dev/qat/include/common/adf_cfg.h index 58502c8605b8..a3ac7678a7a8 100644 --- a/sys/dev/qat/include/common/adf_cfg.h +++ b/sys/dev/qat/include/common/adf_cfg.h @@ -9,6 +9,8 @@ #include "adf_cfg_common.h" #include "adf_cfg_strings.h" +#define ADF_CFG_MAX_VAL 16 + struct adf_cfg_key_val { char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES]; char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES]; @@ -29,6 +31,9 @@ struct adf_cfg_device_data { struct list_head sec_list; struct sysctl_oid *debug; struct sx lock; + char cfg_services[ADF_CFG_MAX_VAL]; + char cfg_mode[ADF_CFG_MAX_VAL]; + u16 num_user_processes; }; struct adf_cfg_depot_list { diff --git a/sys/dev/qat/include/common/adf_cfg_common.h b/sys/dev/qat/include/common/adf_cfg_common.h index 65fc60fc8c3d..d8b1efe3dbe6 100644 --- a/sys/dev/qat/include/common/adf_cfg_common.h +++ b/sys/dev/qat/include/common/adf_cfg_common.h @@ -88,7 +88,10 @@ enum adf_device_type { DEV_200XXVF, DEV_C4XXX, DEV_C4XXXVF, - DEV_4XXX + DEV_D15XX, + DEV_D15XXVF, + DEV_4XXX, + DEV_4XXXVF }; enum adf_cfg_fw_image_type { @@ -196,9 +199,23 @@ struct adf_cfg_instance { #define ADF_CFG_DEF_ASYM_MASK 0x03 #define ADF_CFG_MAX_SERVICES 4 +#define ADF_CTL_IOC_MAGIC 'a' +#define IOCTL_STATUS_ACCEL_DEV \ + _IOWR(ADF_CTL_IOC_MAGIC, 3, struct adf_dev_status_info) +#define IOCTL_RESERVE_RING \ + _IOWR(ADF_CTL_IOC_MAGIC, 10, struct adf_user_reserve_ring) +#define IOCTL_RELEASE_RING \ + _IOWR(ADF_CTL_IOC_MAGIC, 11, struct adf_user_reserve_ring) +#define IOCTL_ENABLE_RING \ + _IOWR(ADF_CTL_IOC_MAGIC, 12, struct adf_user_reserve_ring) +#define IOCTL_DISABLE_RING \ + _IOWR(ADF_CTL_IOC_MAGIC, 13, struct adf_user_reserve_ring) +#define IOCTL_GET_NUM_DEVICES _IOR(ADF_CTL_IOC_MAGIC, 4, int32_t) #define ADF_CFG_HB_DEFAULT_VALUE 500 #define ADF_CFG_HB_COUNT_THRESHOLD 3 #define ADF_MIN_HB_TIMER_MS 100 +#define IOCTL_GET_CFG_VAL \ + _IOW(ADF_CTL_IOC_MAGIC, 5, struct adf_user_cfg_ctl_data) enum adf_device_heartbeat_status { DEV_HB_UNRESPONSIVE = 0, @@ -210,4 +227,6 @@ struct adf_dev_heartbeat_status_ctl { uint16_t device_id; enum adf_device_heartbeat_status status; }; +#define IOCTL_HEARTBEAT_ACCEL_DEV \ *** 27173 LINES SKIPPED ***
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