From owner-svn-src-stable@FreeBSD.ORG Sun Oct 26 04:17:21 2014 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id B4963EF7; Sun, 26 Oct 2014 04:17:21 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 81B58661; Sun, 26 Oct 2014 04:17:21 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s9Q4HLO0044594; Sun, 26 Oct 2014 04:17:21 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s9Q4HLvo044593; Sun, 26 Oct 2014 04:17:21 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201410260417.s9Q4HLvo044593@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sun, 26 Oct 2014 04:17:21 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r273682 - stable/10/sys/arm/freescale/imx X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Oct 2014 04:17:22 -0000 Author: ian Date: Sun Oct 26 04:17:20 2014 New Revision: 273682 URL: https://svnweb.freebsd.org/changeset/base/273682 Log: MFC r273353, r273514: Attach the imx6 CCM driver during BUS_PASS_CPU. Unconditionally enable the clocks for all imx6 devices that we have drivers for, or that are required to run the chip (such as busses). Modified: stable/10/sys/arm/freescale/imx/imx6_ccm.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/freescale/imx/imx6_ccm.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_ccm.c Sun Oct 26 04:15:27 2014 (r273681) +++ stable/10/sys/arm/freescale/imx/imx6_ccm.c Sun Oct 26 04:17:20 2014 (r273682) @@ -76,6 +76,28 @@ WR4(struct ccm_softc *sc, bus_size_t off bus_write_4(sc->mem_res, off, val); } +/* + * Until we have a fully functional ccm driver which implements the fdt_clock + * interface, use the age-old workaround of unconditionally enabling the clocks + * for devices we might need to use. The SoC defaults to most clocks enabled, + * but the rom boot code and u-boot disable a few of them. We turn on only + * what's needed to run the chip plus devices we have drivers for, and turn off + * devices we don't yet have drivers for. (Note that USB is not turned on here + * because that is one we do when the driver asks for it.) + */ +static void +ccm_init_gates(struct ccm_softc *sc) +{ + /* Turns on... */ + WR4(sc, CCM_CCGR0, 0x0000003f); /* ahpbdma, aipstz 1 & 2 busses */ + WR4(sc, CCM_CCGR1, 0x00300c00); /* gpt, enet */ + WR4(sc, CCM_CCGR2, 0x0fffffc0); /* ipmux & ipsync (bridges), iomux, i2c */ + WR4(sc, CCM_CCGR3, 0x3ff00000); /* DDR memory controller */ + WR4(sc, CCM_CCGR4, 0x0000f300); /* pl301 bus crossbar */ + WR4(sc, CCM_CCGR5, 0x0f000000); /* uarts */ + WR4(sc, CCM_CCGR6, 0x000000cc); /* usdhc 1 & 3 */ +} + static int ccm_detach(device_t dev) { @@ -130,6 +152,8 @@ ccm_attach(device_t dev) reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; WR4(sc, CCM_CLPCR, reg); + ccm_init_gates(sc); + err = 0; out: @@ -261,5 +285,6 @@ static driver_t ccm_driver = { static devclass_t ccm_devclass; -DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0); +EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0, + BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);