From owner-svn-src-all@FreeBSD.ORG Mon Mar 9 14:42:26 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id BF41960B; Mon, 9 Mar 2015 14:42:26 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id AAD83208; Mon, 9 Mar 2015 14:42:26 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t29EgQGV051907; Mon, 9 Mar 2015 14:42:26 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t29EgQlq051906; Mon, 9 Mar 2015 14:42:26 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201503091442.t29EgQlq051906@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Mon, 9 Mar 2015 14:42:26 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279810 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Mar 2015 14:42:26 -0000 Author: ian Date: Mon Mar 9 14:42:25 2015 New Revision: 279810 URL: https://svnweb.freebsd.org/changeset/base/279810 Log: Clean data cache before instruction cache in armv7_icache_sync_range(). Also ensure dsb precedes isb in all icache maintenance routines (first do a data sync, then stall the instruction stream until it finishes). Submitted by: Michal Meloun Modified: head/sys/arm/arm/cpufunc_asm_armv7.S Modified: head/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv7.S Mon Mar 9 14:01:35 2015 (r279809) +++ head/sys/arm/arm/cpufunc_asm_armv7.S Mon Mar 9 14:42:25 2015 (r279810) @@ -247,8 +247,8 @@ ENTRY(armv7_idcache_wbinv_range) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_id_wbinv_next - isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ + isb /* instruction synchronization barrier */ RET END(armv7_idcache_wbinv_range) @@ -258,8 +258,8 @@ ENTRY_NP(armv7_icache_sync_all) #else mcr CP15_ICIALLU #endif - isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ + isb /* instruction synchronization barrier */ RET END(armv7_icache_sync_all) @@ -267,13 +267,13 @@ ENTRY_NP(armv7_icache_sync_range) ldr ip, .Larmv7_icache_line_size ldr ip, [ip] .Larmv7_sync_next: - mcr CP15_ICIMVAU(r0) mcr CP15_DCCMVAC(r0) + mcr CP15_ICIMVAU(r0) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_sync_next - isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ + isb /* instruction synchronization barrier */ RET END(armv7_icache_sync_range)