From owner-svn-src-head@freebsd.org Wed Oct 30 14:05:51 2019 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 915DE1A63BD; Wed, 30 Oct 2019 14:05:51 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4739GR37zyz3yhQ; Wed, 30 Oct 2019 14:05:51 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4BE73B5C6; Wed, 30 Oct 2019 14:05:51 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x9UE5pA3043913; Wed, 30 Oct 2019 14:05:51 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x9UE5oe5043911; Wed, 30 Oct 2019 14:05:50 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201910301405.x9UE5oe5043911@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Wed, 30 Oct 2019 14:05:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r354179 - in head/sys/arm64: arm64 include X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys/arm64: arm64 include X-SVN-Commit-Revision: 354179 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Oct 2019 14:05:51 -0000 Author: andrew Date: Wed Oct 30 14:05:50 2019 New Revision: 354179 URL: https://svnweb.freebsd.org/changeset/base/354179 Log: Allow exceptions to be masked when in userspace We may want to mask exceptions when in userspace. This was previously impossible as threads are created with all exceptions unmasked and signals expected userspace to mask any. Fix these by copying the mask state on thread creation and allow exceptions to be masked on signal return, as long as they don't change. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/arm64/machdep.c head/sys/arm64/arm64/vm_machdep.c head/sys/arm64/include/armreg.h Modified: head/sys/arm64/arm64/machdep.c ============================================================================== --- head/sys/arm64/arm64/machdep.c Wed Oct 30 13:45:40 2019 (r354178) +++ head/sys/arm64/arm64/machdep.c Wed Oct 30 14:05:50 2019 (r354179) @@ -441,7 +441,8 @@ set_mcontext(struct thread *td, mcontext_t *mcp) spsr = mcp->mc_gpregs.gp_spsr; if ((spsr & PSR_M_MASK) != PSR_M_EL0t || - (spsr & (PSR_AARCH32 | PSR_F | PSR_I | PSR_A | PSR_D)) != 0) + (spsr & PSR_AARCH32) != 0 || + (spsr & PSR_DAIF) != (td->td_frame->tf_spsr & PSR_DAIF)) return (EINVAL); memcpy(tf->tf_x, mcp->mc_gpregs.gp_x, sizeof(tf->tf_x)); Modified: head/sys/arm64/arm64/vm_machdep.c ============================================================================== --- head/sys/arm64/arm64/vm_machdep.c Wed Oct 30 13:45:40 2019 (r354178) +++ head/sys/arm64/arm64/vm_machdep.c Wed Oct 30 14:05:50 2019 (r354179) @@ -98,7 +98,7 @@ cpu_fork(struct thread *td1, struct proc *p2, struct t bcopy(td1->td_frame, tf, sizeof(*tf)); tf->tf_x[0] = 0; tf->tf_x[1] = 0; - tf->tf_spsr = td1->td_frame->tf_spsr & PSR_M_32; + tf->tf_spsr = td1->td_frame->tf_spsr & (PSR_M_32 | PSR_DAIF); td2->td_frame = tf; Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Wed Oct 30 13:45:40 2019 (r354178) +++ head/sys/arm64/include/armreg.h Wed Oct 30 14:05:50 2019 (r354179) @@ -608,6 +608,7 @@ #define PSR_I 0x00000080 #define PSR_A 0x00000100 #define PSR_D 0x00000200 +#define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) #define PSR_IL 0x00100000 #define PSR_SS 0x00200000 #define PSR_V 0x10000000