From owner-dev-commits-src-all@freebsd.org Thu Feb 18 21:21:40 2021 Return-Path: Delivered-To: dev-commits-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 55C8B54F775; Thu, 18 Feb 2021 21:21:40 +0000 (UTC) (envelope-from mhorne@freebsd.org) Received: from smtp.freebsd.org (smtp.freebsd.org [IPv6:2610:1c1:1:606c::24b:4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "smtp.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4DhSM81zX2z3pKC; Thu, 18 Feb 2021 21:21:40 +0000 (UTC) (envelope-from mhorne@freebsd.org) Received: from mail-yb1-f173.google.com (mail-yb1-f173.google.com [209.85.219.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "GTS CA 1O1" (verified OK)) (Authenticated sender: mhorne) by smtp.freebsd.org (Postfix) with ESMTPSA id 36E619A53; Thu, 18 Feb 2021 21:21:40 +0000 (UTC) (envelope-from mhorne@freebsd.org) Received: by mail-yb1-f173.google.com with SMTP id p186so3589469ybg.2; Thu, 18 Feb 2021 13:21:40 -0800 (PST) X-Gm-Message-State: AOAM533yZKIPGIXfmQO3ZesOmCpnyRNDZGLj5eWRkbgeiniAa2KoNxfR cvhJCkOaBAgxXDZ7B31c1SxFbf2DoHpVzCp+pTs= X-Google-Smtp-Source: ABdhPJxknUZhqO1EnqRePs4OJhU2FQ03xalH1urA/pk4ZQQOsDF++eHGX6SM5S+FSKprg0+pmz0ekP8nTPZsgqnCetc= X-Received: by 2002:a05:6902:4b2:: with SMTP id r18mr9622528ybs.226.1613683299756; Thu, 18 Feb 2021 13:21:39 -0800 (PST) MIME-Version: 1.0 References: <202102182119.11ILJaaE098874@gitrepo.freebsd.org> In-Reply-To: <202102182119.11ILJaaE098874@gitrepo.freebsd.org> From: Mitchell Horne Date: Thu, 18 Feb 2021 17:21:28 -0400 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: git: 04d2d2d7fd22 - main - cgem: improve usage of busdma(9) KPI To: Mitchell Horne Cc: src-committers , dev-commits-src-all@freebsd.org, dev-commits-src-main@freebsd.org Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev-commits-src-all@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commit messages for all branches of the src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Feb 2021 21:21:40 -0000 On Thu, Feb 18, 2021 at 5:19 PM Mitchell Horne wrote: > > The branch main has been updated by mhorne: > > URL: https://cgit.FreeBSD.org/src/commit/?id=04d2d2d7fd22bba638ccb5a0b2e0805087a70cd3 > > commit 04d2d2d7fd22bba638ccb5a0b2e0805087a70cd3 > Author: Mitchell Horne > AuthorDate: 2021-01-20 15:07:53 +0000 > Commit: Mitchell Horne > CommitDate: 2021-02-18 21:17:41 +0000 > > cgem: improve usage of busdma(9) KPI > > BUS_DMA_NOCACHE should only be used when one needs to guarantee the > created mapping has uncached memory attributes, usually as a result > of buggy hardware. Normal use cases should pass BUS_DMA_COHERENT, to > create an appropriate mapping based on the flags passed to > bus_dma_tag_create(). > > This should have no functional change, since the DMA tags in this driver > are created without the BUS_DMA_COHERENT flag. > > Reported by: mmel > Reviewed by: mmel, Thomas Skibo > MFC after: 3 days Whoops, forgot to include: Differential Revision: https://reviews.freebsd.org/D28775 > --- > sys/dev/cadence/if_cgem.c | 12 ++++-------- > 1 file changed, 4 insertions(+), 8 deletions(-) > > diff --git a/sys/dev/cadence/if_cgem.c b/sys/dev/cadence/if_cgem.c > index 81fc39b831af..0583e846458a 100644 > --- a/sys/dev/cadence/if_cgem.c > +++ b/sys/dev/cadence/if_cgem.c > @@ -443,17 +443,13 @@ cgem_setup_descs(struct cgem_softc *sc) > return (err); > > /* > - * Allocate DMA memory in non-cacheable space. We allocate transmit, > - * receive and null descriptor queues all at once because the > - * hardware only provides one register for the upper 32 bits of > - * rx and tx descriptor queues hardware addresses. > + * Allocate DMA memory. We allocate transmit, receive and null > + * descriptor queues all at once because the hardware only provides > + * one register for the upper 32 bits of rx and tx descriptor queues > + * hardware addresses. > */ > err = bus_dmamem_alloc(sc->desc_dma_tag, (void **)&sc->rxring, > -#ifdef __arm__ > BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, > -#else > - BUS_DMA_NOWAIT | BUS_DMA_NOCACHE | BUS_DMA_ZERO, > -#endif > &sc->rxring_dma_map); > if (err) > return (err);