From owner-freebsd-mips@FreeBSD.ORG Sat Mar 17 21:29:30 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1AEEB106564A for ; Sat, 17 Mar 2012 21:29:30 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pz0-f54.google.com (mail-pz0-f54.google.com [209.85.210.54]) by mx1.freebsd.org (Postfix) with ESMTP id E53828FC1F for ; Sat, 17 Mar 2012 21:29:29 +0000 (UTC) Received: by dald2 with SMTP id d2so8460516dal.13 for ; Sat, 17 Mar 2012 14:29:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:content-type; bh=mdKOKZJ/7PPJI/ifA8wMx/S/8QAGg/iOlnMmrxLGg8Q=; b=PW2LuI+mPkkfPpLAfv3hEp4k6CS30magVI4uas5plNxFKjv4eKE9eeJiz9ujDVM9/X LSDyelCWTnnAFPrTBPTk6d/YXbayE+rfKO9LFsIP0GsC0GTYxFG6m3goxyrQl/wHSLbM 258YnjWb+nhCG1xNpqkf1pTvwrFKMAxEx9C0V7EijoYzgyy7jXU6aR7x+SPB8BJG72kE Uwim2JSanN7kBfH80DeK9gAapvkKxscV3I36p95HnBS/idf3OpKyawsnZUBBp+wrZ5cX /ARhj732sG4Hgic/tAORWE4AxtivWbcyd2JF8aSTfSb0SeyoV/C2AgOWDLBb8ufoqfF4 /tpA== MIME-Version: 1.0 Received: by 10.68.231.66 with SMTP id te2mr18452738pbc.42.1332019769534; Sat, 17 Mar 2012 14:29:29 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.143.33.5 with HTTP; Sat, 17 Mar 2012 14:29:29 -0700 (PDT) Date: Sat, 17 Mar 2012 14:29:29 -0700 X-Google-Sender-Auth: 8o0YSQ8M653IwUe1BmikbTQQA6s Message-ID: From: Adrian Chadd To: freebsd-mips@freebsd.org Content-Type: text/plain; charset=ISO-8859-1 Subject: arge/switch roadmap: my plans X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Mar 2012 21:29:30 -0000 Hi, There's been a lot of great work done by quite a few of you but I think now it's time to finalise something that's usable right now and that we can (hopefully) build upon. Here's what I'm going to do: * I'm going to separate out arge into the MII bus part and the ethernet controller part. I'm not sure whether that'll be an "arge controller" that supports the MII bus, then the ethernet controller is a child of that.. or whether I have two separate devices with suitable locking and enforce the probe/attach order somehow, I'm not sure. Suffice to say, I'm going to do that split. I realise that's not the "right" solution for all the PHY<->MDIOBUS mapping that's going on but it solves our immediate problem with this mess. * I'm then going to remove the phymask stuff from arge and rely on the miibus phymask code. * I'm going to introduce a new configuration option for arge which specifies whether to use a forced media/duplex setting and no PHY (to support current setups) or to attach an MII device. * I'm going to introduce a new configuration option for arge which specifies whether to ignore the MII clock (as is right now), or force it to something, or lock it to the port speed settings. That should keep Pat happy. * I'm going to undo the arge hack that makes arge0/arge1 MDIO register access map to arge0 only (which is only true for ar71xx), so AR724x and AR913x configurations become possible. At this point AR71xx boards that have multiple PHYs will need configuration changes as they'll have multiple PHYs on the same bus. This last step will break boards which have a PHY for arge1 - for example, the PB47. We'll need a way to be able to say that the PHY for arge1 is actually on argec0 rather than argec1. At this point we can start integrating switch PHY support. Any questions/comments/issues? Adrian