Date: Wed, 17 Mar 2010 14:30:29 GMT From: Rafal Jaworowski <raj@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 175762 for review Message-ID: <201003171430.o2HEUTiG033551@repoman.freebsd.org>
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http://p4web.freebsd.org/chv.cgi?CH=175762 Change 175762 by raj@raj_nand on 2010/03/17 14:30:17 Extend MPC85XX LBC driver towards NAND controller support. NAND controller engine is integral part of the LBC unit in MPC8572 and QorIQ systems. Affected files ... .. //depot/projects/nand2/sys/powerpc/mpc85xx/lbc.c#2 edit .. //depot/projects/nand2/sys/powerpc/mpc85xx/lbc.h#2 edit Differences ... ==== //depot/projects/nand2/sys/powerpc/mpc85xx/lbc.c#2 (text+ko) ==== @@ -34,8 +34,10 @@ #include <sys/systm.h> #include <sys/ktr.h> #include <sys/kernel.h> +#include <sys/lock.h> #include <sys/malloc.h> #include <sys/module.h> +#include <sys/mutex.h> #include <sys/bus.h> #include <sys/rman.h> #include <machine/bus.h> @@ -58,6 +60,9 @@ struct rman sc_rman; vm_offset_t sc_kva[LBC_DEV_MAX]; + + struct mtx sc_regs_mtx; + }; struct lbc_devinfo { @@ -88,7 +93,14 @@ LBCRES_MSEL_GPCM, LBCRES_DECC_DISABLED, LBCRES_ATOM_DISABLED, 0 }, - + /* + * (0x008000 - SP, 0x040000 - LP + */ + { + LBC_DEVTYPE_NAND, 2, 0xffa00000, 0x00040000, 8, + LBCRES_MSEL_FCM, LBCRES_DECC_RMW, + LBCRES_ATOM_DISABLED, 0 + }, {0} }; @@ -136,6 +148,7 @@ devclass_t lbc_devclass; DRIVER_MODULE(lbc, ocpbus, lbc_driver, lbc_devclass, 0, 0); + static __inline void lbc_write_reg(struct lbc_softc *sc, bus_size_t off, uint32_t val) { @@ -260,7 +273,6 @@ regbuff |= (res->lbr_msel << 5); regbuff |= (res->lbr_atom << 2); regbuff |= 1; - lbc_write_reg(sc, LBC85XX_BR(unit), regbuff); /* @@ -275,9 +287,15 @@ regbuff |= 0x00000ff7; break; case LBCRES_MSEL_FCM: - printf("FCM mode not supported yet!"); - error = ENOSYS; - goto fail; + /* + * Options register setup for FCM: + * - Large Page device, + * - relaxed timing + * + * TODO Add flag support for options register + */ + regbuff |= 0x0796; + break; case LBCRES_MSEL_UPMA: case LBCRES_MSEL_UPMB: case LBCRES_MSEL_UPMC: @@ -323,7 +341,7 @@ struct lbc_softc *sc; struct rman *rm; const struct lbc_resource *lbcres; - int error; + int error, i; sc = device_get_softc(dev); sc->sc_dev = dev; @@ -352,6 +370,13 @@ goto fail; } + /* clear BRs & ORs, from anything that could remain from uboot */ + for (i = 0; i <= 7; i++) { + lbc_write_reg(sc, LBC85XX_BR(i), 0); + lbc_write_reg(sc, LBC85XX_OR(i), 0); + } + /* initialize mutex */ + mtx_init(&sc->sc_regs_mtx, "lbc_reg_access_mtx", NULL, MTX_DEF); /* * Initialize configuration register: * - enable Local Bus @@ -422,7 +447,6 @@ if (error) return (NULL); } - error = lbc_get_resource(dev, child, type, *rid, &start, &count); if (error) return (NULL); @@ -515,6 +539,7 @@ switch (dinfo->lbc_devtype) { case LBC_DEVTYPE_CFI: + case LBC_DEVTYPE_NAND: case LBC_DEVTYPE_RTC: for (; lbcres->lbr_devtype; lbcres++) { if (dinfo->lbc_unit == lbcres->lbr_unit) { @@ -528,3 +553,31 @@ } return (0); } + +void +lbc_set_register(device_t dev, bus_size_t offs, uint32_t val) +{ + struct lbc_softc *sc; + device_t lbcd; + + lbcd = device_get_parent(dev); + sc = (struct lbc_softc *)(device_get_softc(lbcd)); + mtx_lock(&sc->sc_regs_mtx); + bus_space_write_4(sc->sc_bst, sc->sc_bsh, offs, val); + mtx_unlock(&sc->sc_regs_mtx); +} + +uint32_t +lbc_get_register(device_t dev, bus_size_t offs) +{ + struct lbc_softc *sc; + device_t lbcd; + uint32_t retval; + + lbcd = device_get_parent(dev); + sc = (struct lbc_softc *)(device_get_softc(lbcd)); + mtx_lock(&sc->sc_regs_mtx); + retval = bus_space_read_4(sc->sc_bst, sc->sc_bsh, offs); + mtx_unlock(&sc->sc_regs_mtx); + return retval; +} ==== //depot/projects/nand2/sys/powerpc/mpc85xx/lbc.h#2 (text+ko) ==== @@ -34,15 +34,33 @@ /* Maximum number of devices on Local Bus */ #define LBC_DEV_MAX 8 +/* Maximum number of device types that can be connected to Local Bus */ +#define LBC_DEV_TYPES_MAX 3 + /* Device types. */ #define LBC_DEVTYPE_CFI 1 #define LBC_DEVTYPE_RTC 2 +#define LBC_DEVTYPE_NAND 3 /* Local access registers */ #define LBC85XX_BR(n) (8 * n) #define LBC85XX_OR(n) (4 + (8 * n)) +#define LBC85XX_MRTPR (0x84) +#define LBC85XX_MDR (0x88) +#define LBC85XX_LSOR (0x90) +#define LBC85XX_LTESR (0xb0) +#define LBC85XX_LTEDR (0xb4) +#define LBC85XX_LTEIR (0xb8) +#define LBC85XX_LTEATR (0xbC) +#define LBC85XX_LTEAR (0xc0) #define LBC85XX_LBCR (0xd0) #define LBC85XX_LCRR (0xd4) +#define LBC85XX_FMR (0xe0) +#define LBC85XX_FIR (0xe4) +#define LBC85XX_FCR (0xe8) +#define LBC85XX_FBAR (0xeC) +#define LBC85XX_FPAR (0xf0) +#define LBC85XX_FBCR (0xf4) /* LBC machine select */ #define LBCRES_MSEL_GPCM 0 @@ -74,5 +92,7 @@ }; extern const struct lbc_resource mpc85xx_lbc_resources[]; +void lbc_set_register(device_t dev, bus_size_t offs, uint32_t val); +uint32_t lbc_get_register(device_t dev, bus_size_t offs); #endif /* _MACHINE_LBC_H_ */
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