From owner-freebsd-mips@FreeBSD.ORG Tue Sep 14 05:33:54 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 16D3F106566B for ; Tue, 14 Sep 2010 05:33:54 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-wy0-f182.google.com (mail-wy0-f182.google.com [74.125.82.182]) by mx1.freebsd.org (Postfix) with ESMTP id A0F9B8FC14 for ; Tue, 14 Sep 2010 05:33:53 +0000 (UTC) Received: by wyb33 with SMTP id 33so8272286wyb.13 for ; Mon, 13 Sep 2010 22:33:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=ao07KVgS/4+HE6dKKMhKSjcTotjpXLhn5I1P+R3jSSM=; b=adcq4Fc911oogPa3Y5s2vT8BXM6MUhrgOa9Hf/drw4HPP8pVKutKUyspFzDe+lRHnN SSpiF/dlsUTrIYuzzCWTa3JNc2n4P5XK9dHn0NO201P/tWZlHpfaE2KODZxDqTMuF3Jm wDmHAUpfwM3ynXB4J4MEsfVQEh1HfOmpCrKMA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=dDIzVYmBGHipv8xKljNUjNEAN8mWKZEzDr+u1jv66bfYldLNDS1o/aPyZ251b/QSsj EQIWWLObjx6998zC3Jqr7xwft2M4lQDWC3jsrTI145CdjUyOy+inCxUcC9M6yRxzGeds YlMO/dtRm1OvBTbZ5v2m6PYax70D060LNBolA= MIME-Version: 1.0 Received: by 10.216.17.9 with SMTP id i9mr3465600wei.80.1284442432642; Mon, 13 Sep 2010 22:33:52 -0700 (PDT) Received: by 10.216.171.12 with HTTP; Mon, 13 Sep 2010 22:33:52 -0700 (PDT) In-Reply-To: References: Date: Tue, 14 Sep 2010 11:03:52 +0530 Message-ID: From: "Jayachandran C." To: Neel Natu Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: PATCH: make usage of set_intr_mask() sane X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Sep 2010 05:33:54 -0000 On Tue, Sep 14, 2010 at 7:37 AM, Neel Natu wrote: > Hi, > > This patch changes the meaning of the 'mask' argument to > 'set_intr_mask(mask)' to exactly match the meaning of the IM0..7 bits > in the CP0 status register. > > The way we have it set up right now is exactly the opposite for no > good reason IMHO. > > Please review and let me know if there are any objections. This is something I thought about doing with the last patch - so I would like to see this go in. But I think the reason probably is that on MIPS setting interrupt mask bit to 1 enables the interrupt, instead of masking (disabling) it. JC. > best > Neel > > Index: sys/mips/sibyte/sb_machdep.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- sys/mips/sibyte/sb_machdep.c =A0 =A0 =A0 =A0(revision 212587) > +++ sys/mips/sibyte/sb_machdep.c =A0 =A0 =A0 =A0(working copy) > @@ -370,7 +370,7 @@ > =A0 =A0 =A0 =A0 */ > =A0 =A0 =A0 =A0clock_int_mask =3D hard_int_mask(5); > =A0 =A0 =A0 =A0ipi_int_mask =3D hard_int_mask(platform_ipi_intrnum()); > - =A0 =A0 =A0 set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int= _mask)); > + =A0 =A0 =A0 set_intr_mask(ipi_int_mask | clock_int_mask); > =A0} > > =A0int > Index: sys/mips/include/cpufunc.h > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- sys/mips/include/cpufunc.h =A0(revision 212587) > +++ sys/mips/include/cpufunc.h =A0(working copy) > @@ -272,7 +272,7 @@ > =A0 =A0 =A0 =A0uint32_t ostatus; > > =A0 =A0 =A0 =A0ostatus =3D mips_rd_status(); > - =A0 =A0 =A0 mask =3D (ostatus & ~MIPS_SR_INT_MASK) | (~mask & MIPS_SR_I= NT_MASK); > + =A0 =A0 =A0 mask =3D (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_IN= T_MASK); > =A0 =A0 =A0 =A0mips_wr_status(mask); > =A0 =A0 =A0 =A0return (ostatus); > =A0} > Index: sys/mips/cavium/octeon_mp.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- sys/mips/cavium/octeon_mp.c (revision 212587) > +++ sys/mips/cavium/octeon_mp.c (working copy) > @@ -96,7 +96,7 @@ > =A0 =A0 =A0 =A0 */ > =A0 =A0 =A0 =A0clock_int_mask =3D hard_int_mask(5); > =A0 =A0 =A0 =A0ipi_int_mask =3D hard_int_mask(platform_ipi_intrnum()); > - =A0 =A0 =A0 set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int= _mask)); > + =A0 =A0 =A0 set_intr_mask(ipi_int_mask | clock_int_mask); > > =A0 =A0 =A0 =A0mips_wbflush(); > =A0} > Index: sys/mips/mips/machdep.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- sys/mips/mips/machdep.c =A0 =A0 (revision 212587) > +++ sys/mips/mips/machdep.c =A0 =A0 (working copy) > @@ -356,7 +356,7 @@ > =A0 =A0 =A0 =A0 * Mask all interrupts. Each interrupt will be enabled > =A0 =A0 =A0 =A0 * when handler is installed for it > =A0 =A0 =A0 =A0 */ > - =A0 =A0 =A0 set_intr_mask(MIPS_SR_INT_MASK); > + =A0 =A0 =A0 set_intr_mask(0); > > =A0 =A0 =A0 =A0/* Clear BEV in SR so we start handling our own exceptions= */ > =A0 =A0 =A0 =A0mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV); > Index: sys/mips/mips/trap.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- sys/mips/mips/trap.c =A0 =A0 =A0 =A0(revision 212587) > +++ sys/mips/mips/trap.c =A0 =A0 =A0 =A0(working copy) > @@ -304,7 +304,7 @@ > =A0 =A0 =A0 =A0 * return to userland. > =A0 =A0 =A0 =A0 */ > =A0 =A0 =A0 =A0if (trapframe->sr & MIPS_SR_INT_IE) { > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 set_intr_mask(~(trapframe->sr & MIPS_SR_INT= _MASK)); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 set_intr_mask(trapframe->sr & MIPS_SR_INT_M= ASK); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0intr_enable(); > =A0 =A0 =A0 =A0} else { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0intr_disable(); > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.org" >