From owner-svn-src-head@freebsd.org Mon Dec 14 16:07:21 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CF78FA43E78; Mon, 14 Dec 2015 16:07:21 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8941C1B9B; Mon, 14 Dec 2015 16:07:21 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tBEG7Kud041633; Mon, 14 Dec 2015 16:07:20 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tBEG7KpJ041632; Mon, 14 Dec 2015 16:07:20 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201512141607.tBEG7KpJ041632@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Mon, 14 Dec 2015 16:07:20 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r292214 - head/sys/arm64/arm64 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Dec 2015 16:07:21 -0000 Author: andrew Date: Mon Dec 14 16:07:20 2015 New Revision: 292214 URL: https://svnweb.freebsd.org/changeset/base/292214 Log: Add support for MSI interrupts to the gicv2m controller. The allocation is still quite simplistic, it just increments a counter to use the next interrupt. Obtained from: ABT Systems Ltd Sponsored by: SoftIron Inc Modified: head/sys/arm64/arm64/gic.c Modified: head/sys/arm64/arm64/gic.c ============================================================================== --- head/sys/arm64/arm64/gic.c Mon Dec 14 15:45:11 2015 (r292213) +++ head/sys/arm64/arm64/gic.c Mon Dec 14 16:07:20 2015 (r292214) @@ -432,6 +432,39 @@ gicv2m_alloc_msix(device_t dev, device_t } static int +gicv2m_alloc_msi(device_t dev, device_t pci_dev, int count, int *irqs) +{ + struct arm_gic_softc *psc; + struct gicv2m_softc *sc; + uint32_t reg; + int i, irq; + + psc = device_get_softc(device_get_parent(dev)); + sc = device_get_softc(dev); + + mtx_lock(&sc->sc_mutex); + KASSERT(sc->sc_spi_offset + count <= sc->sc_spi_count, + ("No free SPIs for %d MSI interrupts", count)); + + /* Find an unused interrupt */ + for (i = 0; i < count; i++) { + irq = sc->sc_spi_start + sc->sc_spi_offset; + sc->sc_spi_offset++; + + /* Interrupts need to be edge triggered, set this */ + reg = gic_d_read_4(psc, GICD_ICFGR(irq >> 4)); + reg |= (GICD_ICFGR_TRIG_EDGE | GICD_ICFGR_POL_HIGH) << + ((irq & 0xf) * 2); + gic_d_write_4(psc, GICD_ICFGR(irq >> 4), reg); + + irqs[i] = irq; + } + mtx_unlock(&sc->sc_mutex); + + return (0); +} + +static int gicv2m_map_msi(device_t dev, device_t pci_dev, int irq, uint64_t *addr, uint32_t *data) { @@ -448,8 +481,9 @@ static device_method_t arm_gicv2m_method DEVMETHOD(device_probe, gicv2m_probe), DEVMETHOD(device_attach, gicv2m_attach), - /* MSI-X */ + /* MSI/MSI-X */ DEVMETHOD(pic_alloc_msix, gicv2m_alloc_msix), + DEVMETHOD(pic_alloc_msi, gicv2m_alloc_msi), DEVMETHOD(pic_map_msi, gicv2m_map_msi), { 0, 0 }