From owner-freebsd-stable@FreeBSD.ORG Wed Sep 9 21:05:26 2009 Return-Path: Delivered-To: freebsd-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 0A1B3106566B; Wed, 9 Sep 2009 21:05:26 +0000 (UTC) (envelope-from luigi@onelab2.iet.unipi.it) Received: from onelab2.iet.unipi.it (onelab2.iet.unipi.it [131.114.59.238]) by mx1.freebsd.org (Postfix) with ESMTP id BF9098FC12; Wed, 9 Sep 2009 21:05:25 +0000 (UTC) Received: by onelab2.iet.unipi.it (Postfix, from userid 275) id 9B814730DA; Wed, 9 Sep 2009 23:11:23 +0200 (CEST) Date: Wed, 9 Sep 2009 23:11:23 +0200 From: Luigi Rizzo To: John Baldwin Message-ID: <20090909211123.GD93761@onelab2.iet.unipi.it> References: <20090906155154.GA8283@onelab2.iet.unipi.it> <200909091324.53668.jhb@freebsd.org> <20090909203216.GA93761@onelab2.iet.unipi.it> <200909091642.06046.jhb@freebsd.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200909091642.06046.jhb@freebsd.org> User-Agent: Mutt/1.4.2.3i Cc: freebsd-stable@freebsd.org Subject: Re: incorrect usleep/select delays with HZ > 2500 X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Sep 2009 21:05:26 -0000 On Wed, Sep 09, 2009 at 04:42:05PM -0400, John Baldwin wrote: ... > > > It would explain why it gets better later since the uhci(4), ohci(4) and > > > ehci(4) drivers disable the SMI# interrupts while attaching to the > > > controllers. > > > > ok makes sense -- if the SMI interrupts last longer than 1/HZ > > they will cause us to miss one or more wraps of the i8254 in > > $ARCH/isa/clock.c::DELAY(). I suppose with a few measurements > > at different HZ values and some back of the envelope calculations > > one could even determine estimate the frequency and duration > > of those SMI interrupts! > > On recent motherboards I have seen the SMI# interrupt fire every 250 ms with > execution times ranging from 50 us to 1ms for the legacy USB interrupt > handler. We consistently see the TSC frequency miscalculated on the > motherboards with the 1ms duration interrupt. I suspect that the clock that > drives the periodic SMI# interrupt is tied to the i8254 meaning that it often > fires at the same time that the i8254 wraps causing the TSC frequency to > often be wrong. when or even how often it fires should not matter much -- as long as the interrupt is shorter than 1 tick we will be able to see the wrap and handle it correctly. I'll try to write a 1-sec loop around rdtsc() and log large differences in the reads to figure out whether i am getting some long interrupts. cheers luigi