Date: Mon, 4 Feb 2008 14:12:44 GMT From: Oleksandr Tymoshenko <gonzo@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 134779 for review Message-ID: <200802041412.m14ECila084582@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=134779 Change 134779 by gonzo@gonzo_jeeves on 2008/02/04 14:12:06 o Fix MCHECK exception caused by tlbwi instruction in octeon emulation. The solution is to use bogus EntryHi value based on TLB entry index instead of fixed value. Tested by: cognet Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb.S#6 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb.S#6 (text+ko) ==== @@ -81,12 +81,14 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 +#define PAGE_SHIFT 34 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 +#define PAGE_SHIFT 2 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -287,9 +289,15 @@ tlbp # Probe for the entry. MIPS_CPU_NOP_DELAY mfc0 v0, COP_0_TLB_INDEX # See what we got - li t1, MIPS_KSEG0_START # Load invalid entry. + li t1, MIPS_KSEG0_START + 0x0fff0000 bltz v0, 1f # index < 0 => !found nop + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + sll v0, PAGE_SHIFT + 1 + addu t1, v0 _MTC0 t1, COP_0_TLB_HI # Mark entry high as invalid _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry.
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200802041412.m14ECila084582>