From owner-svn-src-head@FreeBSD.ORG Mon Oct 13 16:33:08 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id EF035B19; Mon, 13 Oct 2014 16:33:08 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id DB636D70; Mon, 13 Oct 2014 16:33:08 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s9DGX8vj037021; Mon, 13 Oct 2014 16:33:08 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s9DGX8OJ037020; Mon, 13 Oct 2014 16:33:08 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201410131633.s9DGX8OJ037020@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Mon, 13 Oct 2014 16:33:08 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r273052 - head/sys/arm/ti X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Oct 2014 16:33:09 -0000 Author: andrew Date: Mon Oct 13 16:33:08 2014 New Revision: 273052 URL: https://svnweb.freebsd.org/changeset/base/273052 Log: Use a switch on ti_chip() to find which SoC we are on. This allow us t only enable support for the SoCs we are built for. Modified: head/sys/arm/ti/ti_sdhci.c Modified: head/sys/arm/ti/ti_sdhci.c ============================================================================== --- head/sys/arm/ti/ti_sdhci.c Mon Oct 13 16:23:58 2014 (r273051) +++ head/sys/arm/ti/ti_sdhci.c Mon Oct 13 16:33:08 2014 (r273052) @@ -494,13 +494,21 @@ ti_sdhci_attach(device_t dev) * Set the offset from the device's memory start to the MMCHS registers. * Also for OMAP4 disable high speed mode due to erratum ID i626. */ - if (ti_chip() == CHIP_OMAP_4) { + switch (ti_chip()) { +#ifdef SOC_OMAP4 + case CHIP_OMAP_4: sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; sc->disable_highspeed = true; - } else if (ti_chip() == CHIP_AM335X) + break; +#endif +#ifdef SOC_TI_AM335X + case CHIP_AM335X: sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; - else + break; +#endif + default: panic("Unknown OMAP device\n"); + } /* * The standard SDHCI registers are at a fixed offset (the same on all