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From: Robert Watson <rwatson@FreeBSD.org>
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Subject: PERFORCE change 215042 for review
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http://p4web.freebsd.org/@@215042?ac=10

Change 215042 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/07/28 11:43:17

	Annotate in a comment that the clever MIPS assembly to detect when
	a timer interrupt fires during the run-up to executing a WAIT
	instruction to suspend the processor will need some equally clever
	(perhaps more clever) CP2 code to check PCC once we start running
	multiple security domains in the kernel.  In the mean time, the
	current code should suffice.

Affected files ...

.. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/exception.S#7 edit

Differences ...

==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/exception.S#7 (text+ko) ====

@@ -643,6 +643,11 @@
 
 /*
  * Check for getting interrupts just before wait
+ *
+ * XXXCHERI: Once we use variable CP2 PCC in the kernel, this check will also
+ * need to take that into account.  In the mean time, the fact that we're in
+ * the kernel ring is sufficient to imply that PCC matches the kernel address
+ * space.
  */
 	MFC0	k0, MIPS_COP_0_EXC_PC
 	ori	k0, 0xf