Date: Tue, 03 Sep 2019 14:07:16 -0000 From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r346494 - stable/12/sys/arm/ti Message-ID: <201904211949.x3LJnFoj037530@repo.freebsd.org>
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Author: ian Date: Sun Apr 21 19:49:15 2019 New Revision: 346494 URL: https://svnweb.freebsd.org/changeset/base/346494 Log: MFC r342652: Support the SPI mode and bus clock frequency parameters set by the devices requesting SPI transfers. Modified: stable/12/sys/arm/ti/ti_spi.c Modified: stable/12/sys/arm/ti/ti_spi.c ============================================================================== --- stable/12/sys/arm/ti/ti_spi.c Sun Apr 21 19:30:37 2019 (r346493) +++ stable/12/sys/arm/ti/ti_spi.c Sun Apr 21 19:49:15 2019 (r346494) @@ -446,7 +446,7 @@ ti_spi_transfer(device_t dev, device_t child, struct s { int err; struct ti_spi_softc *sc; - uint32_t reg, cs; + uint32_t clockhz, cs, mode, reg; sc = device_get_softc(dev); @@ -457,6 +457,8 @@ ti_spi_transfer(device_t dev, device_t child, struct s /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); + spibus_get_clock(child, &clockhz); + spibus_get_mode(child, &mode); cs &= ~SPIBUS_CS_HIGH; @@ -466,6 +468,13 @@ ti_spi_transfer(device_t dev, device_t child, struct s return (EINVAL); } + if (mode > 3) + { + device_printf(dev, "Invalid mode %d requested by %s\n", mode, + device_get_nameunit(child)); + return (EINVAL); + } + TI_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ @@ -487,8 +496,8 @@ ti_spi_transfer(device_t dev, device_t child, struct s /* Disable FIFO for now. */ sc->sc_fifolvl = 1; - /* Use a safe clock - 500kHz. */ - ti_spi_set_clock(sc, sc->sc_cs, 500000); + /* Set the bus frequency. */ + ti_spi_set_clock(sc, sc->sc_cs, clockhz); /* Disable the FIFO. */ TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); @@ -500,6 +509,7 @@ ti_spi_transfer(device_t dev, device_t child, struct s MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR | MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS; + reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */ TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); #if 0
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