Date: Tue, 14 May 1996 08:14:38 -0700 From: David Greenman <davidg@Root.COM> To: "matthew c. mead" <mmead@Glock.COM> Cc: joerg_wunsch@uriah.heep.sax.de, blh@nol.net, jgreco@brasil.moneng.mei.com, hackers@freebsd.org, hardware@freebsd.org Subject: Re: Triton chipset with 256k cache caches 32M only? Message-ID: <199605141514.IAA12912@Root.COM> In-Reply-To: Your message of "Tue, 14 May 1996 09:13:28 EDT." <199605141313.JAA07905@Glock.COM>
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>J Wunsch writes: > >> As Brett L. Hawn wrote: > >> > I would highly suggest getting some of the new >> > ASUS (just my particular favorite) tr-2 chipset motherboards, these solve >> > the caching problem along with many of the other inherent bugs of tr-1 >> > chipsets. > >> They even can do ECC now if you're using parity SIMMs! > >> (About to get my new board into service by tomorrow or thursday. :) > > I'd really like to do ECC, I just don't have the money for it right >now. So does this ECC work the same as the ECC on DEC Alphas? On the Alphas, >you put in 5M for every 4M of addressable ram. Is there a fifth simm slot on >these motherboards where a non ECC capable motherboard would have 4? No, it uses the parity bits. Only 8 syndrome bits are needed for 64bit words. -DG David Greenman Core-team/Principal Architect, The FreeBSD Project
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