From owner-svn-src-head@FreeBSD.ORG Mon Nov 21 07:55:37 2011 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BE3E6106564A; Mon, 21 Nov 2011 07:55:37 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id ADD748FC13; Mon, 21 Nov 2011 07:55:37 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id pAL7tbI7030530; Mon, 21 Nov 2011 07:55:37 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id pAL7tbjR030528; Mon, 21 Nov 2011 07:55:37 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201111210755.pAL7tbjR030528@svn.freebsd.org> From: "Jayachandran C." Date: Mon, 21 Nov 2011 07:55:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r227782 - head/sys/mips/include X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Nov 2011 07:55:37 -0000 Author: jchandra Date: Mon Nov 21 07:55:37 2011 New Revision: 227782 URL: http://svn.freebsd.org/changeset/base/227782 Log: XLP processors have the release 2 pagegrain register Add accessors to cpufunc.h Obtained from: prabhath at netlogicmicro com Modified: head/sys/mips/include/cpufunc.h Modified: head/sys/mips/include/cpufunc.h ============================================================================== --- head/sys/mips/include/cpufunc.h Mon Nov 21 07:50:29 2011 (r227781) +++ head/sys/mips/include/cpufunc.h Mon Nov 21 07:55:37 2011 (r227782) @@ -272,6 +272,9 @@ MIPS_RW32_COP0(status, MIPS_COP_0_STATUS MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI); MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); #endif +#ifdef CPU_NLM +MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1); +#endif #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */ MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);