From owner-freebsd-hackers@FreeBSD.ORG Sat Dec 29 23:15:50 2007 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 86B7E16A418 for ; Sat, 29 Dec 2007 23:15:50 +0000 (UTC) (envelope-from perryh@pluto.rain.com) Received: from agora.rdrop.com (agora.rdrop.com [199.26.172.34]) by mx1.freebsd.org (Postfix) with ESMTP id 662C013C44B for ; Sat, 29 Dec 2007 23:15:50 +0000 (UTC) (envelope-from perryh@pluto.rain.com) Received: from agora.rdrop.com (66@localhost [127.0.0.1]) by agora.rdrop.com (8.13.1/8.12.7) with ESMTP id lBTNFl82077160 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 29 Dec 2007 15:15:47 -0800 (PST) (envelope-from perryh@pluto.rain.com) Received: (from uucp@localhost) by agora.rdrop.com (8.13.1/8.12.9/Submit) with UUCP id lBTNFlu6077159; Sat, 29 Dec 2007 15:15:47 -0800 (PST) Received: from fbsd61 by pluto.rain.com (4.1/SMI-4.1-pluto-M2060407) id AA21992; Sat, 29 Dec 07 15:03:12 PST Date: Sat, 29 Dec 2007 15:01:43 -0800 From: perryh@pluto.rain.com To: ivoras@freebsd.org, imp@bsdimp.com Message-Id: <4776d1d7.zI7kRv9uFoaBNKnQ%perryh@pluto.rain.com> References: <20071229.122221.-432830441.imp@bsdimp.com> In-Reply-To: <20071229.122221.-432830441.imp@bsdimp.com> User-Agent: nail 11.25 7/29/05 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: freebsd-hackers@freebsd.org Subject: Re: Architectures with strict alignment? X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 29 Dec 2007 23:15:50 -0000 "M. Warner Losh" wrote: > In message: > Ivan Voras writes: > : Which of the architectures FreeBSD supports (if any) have strict > : memory alignment requirements? (in the sense that accessing a > : 32-bit integer not aligned on a 32-bit address results in a > : hardware trap/exception). > > Sparc64, powerpc, arm, and (thanks to Juniper and others) mips. The degree to which a PowerPC imposes a strict alignment requirement depends on both the particular processor model and the operation being performed. For ordinary integer arithmetic and logical operations, newer PPC processors tend to be more tolerant (although misalignment will typically carry a performance penalty). For the semaphore primitives (lwarx/stwcx.) most PPC will require proper alignment and some will fault if the operand address is cache-inhibited (even though correctly aligned).