Date: Wed, 6 Dec 2006 09:54:48 +0100 From: Olivier Certner <olivier.certner@free.fr> To: freebsd-ia32@freebsd.org Subject: Re: prefetching on pentium4 Message-ID: <200612060954.48736.> In-Reply-To: <20061206042834.59293.qmail@web58611.mail.re3.yahoo.com> References: <20061206042834.59293.qmail@web58611.mail.re3.yahoo.com>
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Hi, On a pentium 4, prefetcht0, prefetcht1 and prefetch2 are identical, at least if you don't have a level 3 cache. Intel's documentation is not very clear about what happens with one more cache in the hierarchy. The prefetchnta instruction does the same thing (fetch some memory bytes into the 2nd level cache) but it is supposed to fetch these bytes in only one way of the cache. I don't know how the way is choosen. Unless you are trying to fetch a relatively large volume of data or data with a special pattern (ie, data that would be put at the same index in the cache, thus utilizing more than one way), you won't see much difference from the prefetchtX variants. You'll have to determine the characteristics of the L2 cache on your paticular P4 processor target in order to check that. Olivier
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