From owner-freebsd-sparc64@freebsd.org Wed Sep 23 20:43:40 2015 Return-Path: Delivered-To: freebsd-sparc64@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 66912A07B0A for ; Wed, 23 Sep 2015 20:43:40 +0000 (UTC) (envelope-from marius@alchemy.franken.de) Received: from alchemy.franken.de (alchemy.franken.de [194.94.249.214]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "alchemy.franken.de", Issuer "alchemy.franken.de" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id ED0DD1A41; Wed, 23 Sep 2015 20:43:39 +0000 (UTC) (envelope-from marius@alchemy.franken.de) Received: from alchemy.franken.de (localhost [127.0.0.1]) by alchemy.franken.de (8.15.2/8.15.2/ALCHEMY.FRANKEN.DE) with ESMTPS id t8NKhabm098749 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 23 Sep 2015 22:43:36 +0200 (CEST) (envelope-from marius@alchemy.franken.de) Received: (from marius@localhost) by alchemy.franken.de (8.15.2/8.15.2/Submit) id t8NKharW098748; Wed, 23 Sep 2015 22:43:36 +0200 (CEST) (envelope-from marius) Date: Wed, 23 Sep 2015 22:43:36 +0200 From: Marius Strobl To: Mark Cave-Ayland Cc: Alexey Dokuchaev , "freebsd-sparc64@freebsd.org" Subject: Re: PCI range checking under qemu-system-sparc64 Message-ID: <20150923204336.GO18789@alchemy.franken.de> References: <20150916031030.GA6711@FreeBSD.org> <55F9C2B8.7030605@ilande.co.uk> <20150916211914.GD18789@alchemy.franken.de> <20150917082817.GA71811@FreeBSD.org> <55FBB662.4080708@ilande.co.uk> <20150919211420.GK18789@alchemy.franken.de> <55FDEA3C.1010804@ilande.co.uk> <20150920043630.GA36162@FreeBSD.org> <20150922221404.GA81100@alchemy.franken.de> <560260A9.9010505@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <560260A9.9010505@ilande.co.uk> User-Agent: Mutt/1.5.23 (2014-03-12) X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.4.3 (alchemy.franken.de [0.0.0.0]); Wed, 23 Sep 2015 22:43:36 +0200 (CEST) X-BeenThere: freebsd-sparc64@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Porting FreeBSD to the Sparc List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Sep 2015 20:43:40 -0000 On Wed, Sep 23, 2015 at 09:19:53AM +0100, Mark Cave-Ayland wrote: > > I've had a quick look through the relevant PDFs and the definitions I > have for tick/stick are this: > > tick: > bit 63: NPT (Non-Privileged Trap enable - defaults to 1) > bits 62 - 0: CPU cycle counter > > tick_cmpr: > bit 63: Interrupt disable (1 = no interrupt) > bits 62 - 0: counter compare value > > stick: > bit 63: Reserved (reads 0, no write) > bits 62 - 0: stick register count value I cannot confirm that, the specification for the first sun4u CPU having a %stick register (UltraSPARC III, see 1, p. 6-105) up to the latest architecture specification (see 2, p. 60) say that bit 32 of %stick is NPT, just as with %tick. Same for the specification the Fujitsu SPARC64 processors follow (3, p. 90). Marius 1: http://www.ece.cmu.edu/~protoflex/lib/exe/fetch.php?media=documentation:usiiiv2.pdf 2: http://www.oracle.com/technetwork/systems/hardware/usparcarchdoc2007-329425.pdf 3: https://www.fujitsu.com/global/Images/JPS1-R1.0.4-Common-pub.pdf