From owner-svn-src-stable@freebsd.org Tue Oct 30 19:10:42 2018 Return-Path: Delivered-To: svn-src-stable@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6A6C110F1A80; Tue, 30 Oct 2018 19:10:42 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 200CD75050; Tue, 30 Oct 2018 19:10:42 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 012232181B; Tue, 30 Oct 2018 19:10:42 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w9UJAfA0030116; Tue, 30 Oct 2018 19:10:41 GMT (envelope-from jhb@FreeBSD.org) Received: (from jhb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w9UJAfxJ030114; Tue, 30 Oct 2018 19:10:41 GMT (envelope-from jhb@FreeBSD.org) Message-Id: <201810301910.w9UJAfxJ030114@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhb set sender to jhb@FreeBSD.org using -f From: John Baldwin Date: Tue, 30 Oct 2018 19:10:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r339928 - stable/11/sys/x86/isa X-SVN-Group: stable-11 X-SVN-Commit-Author: jhb X-SVN-Commit-Paths: stable/11/sys/x86/isa X-SVN-Commit-Revision: 339928 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Oct 2018 19:10:42 -0000 Author: jhb Date: Tue Oct 30 19:10:41 2018 New Revision: 339928 URL: https://svnweb.freebsd.org/changeset/base/339928 Log: MFC 338148: Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an individual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Modified: stable/11/sys/x86/isa/atpic.c stable/11/sys/x86/isa/icu.h Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/x86/isa/atpic.c ============================================================================== --- stable/11/sys/x86/isa/atpic.c Tue Oct 30 18:26:34 2018 (r339927) +++ stable/11/sys/x86/isa/atpic.c Tue Oct 30 19:10:41 2018 (r339928) @@ -73,12 +73,12 @@ __FBSDID("$FreeBSD$"); #define MASTER 0 #define SLAVE 1 +#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq)) + #define NUM_ISA_IRQS 16 static void atpic_init(void *dummy); -unsigned int imen; /* XXX */ - inthand_t IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2), IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5), @@ -99,12 +99,24 @@ inthand_t #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq) -#define ATPIC(io, base, eoi, imenptr) \ - { { atpic_enable_source, atpic_disable_source, (eoi), \ - atpic_enable_intr, atpic_disable_intr, atpic_vector, \ - atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\ - atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \ - (imenptr) } +#define ATPIC(io, base, eoi) { \ + .at_pic = { \ + .pic_enable_source = atpic_enable_source, \ + .pic_disable_source = atpic_disable_source, \ + .pic_eoi_source = (eoi), \ + .pic_enable_intr = atpic_enable_intr, \ + .pic_disable_intr = atpic_disable_intr, \ + .pic_vector = atpic_vector, \ + .pic_source_pending = atpic_source_pending, \ + .pic_resume = atpic_resume, \ + .pic_config_intr = atpic_config_intr, \ + .pic_assign_cpu = atpic_assign_cpu \ + }, \ + .at_ioaddr = (io), \ + .at_irqbase = (base), \ + .at_intbase = IDT_IO_INTS + (base), \ + .at_imen = 0xff, \ + } #define INTSRC(irq) \ { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \ @@ -115,7 +127,7 @@ struct atpic { int at_ioaddr; int at_irqbase; uint8_t at_intbase; - uint8_t *at_imen; + uint8_t at_imen; }; struct atpic_intsrc { @@ -142,8 +154,8 @@ static int atpic_assign_cpu(struct intsrc *isrc, u_int static void i8259_init(struct atpic *pic, int slave); static struct atpic atpics[] = { - ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen), - ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1) + ATPIC(IO_ICU1, 0, atpic_eoi_master), + ATPIC(IO_ICU2, 8, atpic_eoi_slave) }; static struct atpic_intsrc atintrs[] = { @@ -203,9 +215,9 @@ atpic_enable_source(struct intsrc *isrc) struct atpic *ap = (struct atpic *)isrc->is_pic; spinlock_enter(); - if (*ap->at_imen & IMEN_MASK(ai)) { - *ap->at_imen &= ~IMEN_MASK(ai); - outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); + if (ap->at_imen & IMEN_MASK(ai)) { + ap->at_imen &= ~IMEN_MASK(ai); + outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen); } spinlock_exit(); } @@ -218,8 +230,8 @@ atpic_disable_source(struct intsrc *isrc, int eoi) spinlock_enter(); if (ai->at_trigger != INTR_TRIGGER_EDGE) { - *ap->at_imen |= IMEN_MASK(ai); - outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen); + ap->at_imen |= IMEN_MASK(ai); + outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen); } /* @@ -413,7 +425,7 @@ i8259_init(struct atpic *pic, int slave) outb(imr_addr, MASTER_MODE); /* Set interrupt enable mask. */ - outb(imr_addr, *pic->at_imen); + outb(imr_addr, pic->at_imen); /* Reset is finished, default to IRR on read. */ outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR); @@ -433,7 +445,6 @@ atpic_startup(void) int i; /* Start off with all interrupts disabled. */ - imen = 0xffff; i8259_init(&atpics[MASTER], 0); i8259_init(&atpics[SLAVE], 1); atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]); Modified: stable/11/sys/x86/isa/icu.h ============================================================================== --- stable/11/sys/x86/isa/icu.h Tue Oct 30 18:26:34 2018 (r339927) +++ stable/11/sys/x86/isa/icu.h Tue Oct 30 19:10:41 2018 (r339928) @@ -87,7 +87,6 @@ #endif #define IRQ_MASK(irq) (1 << (irq)) -#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq)) void atpic_handle_intr(u_int vector, struct trapframe *frame); void atpic_startup(void);