From owner-freebsd-hackers@FreeBSD.ORG Sat Oct 18 10:00:18 2003 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 3CE4B16A4B3; Sat, 18 Oct 2003 10:00:18 -0700 (PDT) Received: from arginine.spc.org (arginine.spc.org [195.206.69.236]) by mx1.FreeBSD.org (Postfix) with ESMTP id B484843F75; Sat, 18 Oct 2003 10:00:16 -0700 (PDT) (envelope-from bms@spc.org) Received: from localhost (localhost [127.0.0.1]) by arginine.spc.org (Postfix) with ESMTP id 295486543E; Sat, 18 Oct 2003 18:00:15 +0100 (BST) Received: from arginine.spc.org ([127.0.0.1]) by localhost (arginine.spc.org [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 80499-02; Sat, 18 Oct 2003 18:00:14 +0100 (BST) Received: from saboteur.dek.spc.org (unknown [81.3.72.68]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by arginine.spc.org (Postfix) with ESMTP id 15EA16543B; Sat, 18 Oct 2003 18:00:14 +0100 (BST) Received: by saboteur.dek.spc.org (Postfix, from userid 1001) id 4539F27; Sat, 18 Oct 2003 18:00:10 +0100 (BST) Date: Sat, 18 Oct 2003 18:00:10 +0100 From: Bruce M Simpson To: Grumble Message-ID: <20031018170010.GG7662@saboteur.dek.spc.org> Mail-Followup-To: Grumble , freebsd-hackers@freebsd.org, koshy@freebsd.org References: <3F7AA0D8.1080801@kma.eu.org> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="qMm9M+Fa2AknHoGS" Content-Disposition: inline In-Reply-To: <3F7AA0D8.1080801@kma.eu.org> cc: koshy@freebsd.org cc: freebsd-hackers@freebsd.org Subject: Re: Why is PCE not set in CR4? X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 18 Oct 2003 17:00:18 -0000 --qMm9M+Fa2AknHoGS Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Oct 01, 2003 at 11:39:36AM +0200, Grumble wrote: > I have read the perfmon documentation and source code. For several=20 > reasons, I do not think it is totally adequate in my situation. >=20 > It was designed in 1996 with the Pentium Pro in mind, which,=20 > apparently, only has two performance counters: >=20 > #define NPMC 2 > if (pmc < 0 || pmc >=3D NPMC) return EINVAL; [..] > Assume I get perfmon to work with my K7's 4 performance-monitoring=20 > counters. Since PCE is not set, I am not allowed to call RDPMC from=20 > ring 3. I have to make a system call, just to read the counters. I've since read over perfmon and some notes on using performance monitoring counters in "The Indispensable PC Hardware Book". It looks to me as though perfmon *will* do what you want. There isn't really any need to reinvent the wheel. If you want to configure *all* your PMCs to read particular events, then the best way to do this is as follows: Conditionalise the PMC allocation code in perfmon.c to use a boot-time tunable, or an int, which is set by the identcpu.c code. Allocate the PMC structures in perfmon.c at boot-time (or preferably module init time). Then, add the necessary code to perfmon_init() and a new writectlXX() function pertaining to the particular Athlon you're using. > I will pay in terms of computation overhead to process a system=20 > call, instead of a single instruction. But more importantly, it will=20 > wreck the cache, and possibly the TLB. >=20 > There is no point in monitoring an event if the monitoring tools=20 > disturb the environment too much. Ignore the patch I sent previously. perfmon is i386 specific anyway, so hacking perfmon.c is acceptable. What I would suggest instead is to add two new ioctls to perfmon to do this. PMIOGPCE get pce bit value on current CPU PMIOSPCE set pce bit value on current CPU (if superuser) This will allow you to set PMC enable on and off for the uniprocessor case OK, and let you use RDPMC from ring 3. This is not valid for the SMP case, however. Unless you can achieve CPU binding (not affinity) with one of the current scheduler(s) then reading the counters is likely to yield useless results if your code spins across CPUs in an SMP system. An IPI of some kind will be necessary if you want to tell all processors to turn on their PCE bit at the same time. peter@freebsd.org is a good guy to ask about this sort of thing. I'd like to know how you're progressing with this. BMS --qMm9M+Fa2AknHoGS Content-Type: application/pgp-signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Comment: '' iD8DBQE/kXGZueUpAYYNtTsRAmpNAKCYu0Yu48XV/C4ZjhCD7wgx1V03YgCeMR6v wNsQ2mhZIiWO179BI7krrrU= =TzkB -----END PGP SIGNATURE----- --qMm9M+Fa2AknHoGS--