Date: Sun, 20 Mar 2011 09:08:46 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r219794 - head/sys/dev/ath/ath_hal/ar5416 Message-ID: <201103200908.p2K98kxv050503@svn.freebsd.org>
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Author: adrian Date: Sun Mar 20 09:08:45 2011 New Revision: 219794 URL: http://svn.freebsd.org/changeset/base/219794 Log: Cave in and disable the ADC DC gain/offset calibrations if they're not needed. These calibrations are only applicable if the chip operating mode engages both interleaved RX ADCs (ie, it's compensating for the differences in DC gain and DC offset -between- the two ADCs.) Otherwise the chip reads values of 0x0 for the secondary ADC (as I guess it's not enabled here) and thus writes potentially bogus info into the chip. I've tested this on the AR9160 and AR9280; both behave themselves in 11g mode with these calibrations disabled. Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c Sun Mar 20 08:47:59 2011 (r219793) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c Sun Mar 20 09:08:45 2011 (r219794) @@ -72,9 +72,12 @@ ar5416IsCalSupp(struct ath_hal *ah, cons return !IEEE80211_IS_CHAN_B(chan); case ADC_GAIN_CAL: case ADC_DC_CAL: - /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */ - return !IEEE80211_IS_CHAN_B(chan) && - !(IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan)); + /* Run ADC Gain Cal for either 5ghz any or 2ghz HT40 */ + if (IEEE80211_IS_CHAN_2GHZ(chan)) + return AH_FALSE; + if (IEEE80211_IS_CHAN_HT20(chan)) + return AH_FALSE; + return AH_TRUE; } return AH_FALSE; }
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