Date: Tue, 26 Apr 2005 13:20:30 -0400 From: John Baldwin <jhb@FreeBSD.org> To: David Xu <davidxu@FreeBSD.org> Cc: Perforce Change Reviews <perforce@FreeBSD.org> Subject: Re: PERFORCE change 75366 for review Message-ID: <200504261320.31661.jhb@FreeBSD.org> In-Reply-To: <426E43C5.20401@freebsd.org> References: <200504171042.j3HAgeTQ054345@repoman.freebsd.org> <87f1dd37c46f5e61c68035b9989ae5b7@FreeBSD.org> <426E43C5.20401@freebsd.org>
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On Tuesday 26 April 2005 09:36 am, David Xu wrote: > John Baldwin wrote: > > On Apr 17, 2005, at 6:42 AM, David Xu wrote: > >> http://perforce.freebsd.org/chv.cgi?CH=75366 > >> > >> Change 75366 by davidxu@davidxu_alona on 2005/04/17 10:42:05 > >> > >> Implement cpu_set_user_tls for sparc64. > >> > >> Affected files ... > >> > >> .. > >> //depot/projects/davidxu_thread/src/sys/sparc64/sparc64/vm_machdep.c#6 > >> edit > >> > >> Differences ... > >> > >> ==== > >> //depot/projects/davidxu_thread/src/sys/sparc64/sparc64/vm_machdep.c#6 > >> (text+ko) ==== > >> > >> @@ -194,6 +194,15 @@ > >> td->td_retval[1] = tf->tf_out[1]; > >> } > >> > >> +void > >> +cpu_set_user_tls(struct thread *td, void *tls_base, size_t tls_size, > >> + int tls_seg __unused) > >> +{ > >> + if (td == curthread) > >> + flushw(); > >> + td->td_frame->tf_global[7] = tls_base; > >> +} > >> + > > > > I think for at least this one and Alpha you might want a critical > > section in the curthread case like you do on i386 and amd64 since > > calling the Alpha PAL and setting tls_base + flushw() are more than > > one instruction long. > > If this is true, why don't set_mcontext on sparc64 and alpha enter > critical region ? Bugs. :) Actually, sparc64 is probably ok, but alpha_pal_wrunique() on Alpha is basically the same as wrmsr() on x86. You might be ok without a critical section on Alpha but I'm not sure. Actually, I think you are fine. The thread can't get out into userland without resuming and finishing this function first. > I enter critical region on i386 and amd64, because I have to write > global register (amd64 MSR) or gdt on i386, if thread is preempted, > then it may be in intermediate state, for example on amd64: > td->td_pcb->pcb_fsbase = (register_t)tls_base; > ---> > wrmsr(MSR_FSBASE, td->td_pcb->pcb_fsbase); > > if thread is preempted at ---->, a rdmsr in cpu_switch() will overwrite > the value I set before I can write it into MSR_FSBASE register. > > David Xu -- John Baldwin <jhb@FreeBSD.org> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org
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