From owner-freebsd-arm@freebsd.org Mon Jul 31 21:46:20 2017 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id EFE3EDBE84E for ; Mon, 31 Jul 2017 21:46:20 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from pmta2.delivery6.ore.mailhop.org (pmta2.delivery6.ore.mailhop.org [54.200.129.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D47AC6A15C for ; Mon, 31 Jul 2017 21:46:20 +0000 (UTC) (envelope-from ian@freebsd.org) X-MHO-User: 719ffe91-7639-11e7-a4a1-c9e62e5d9688 X-Report-Abuse-To: https://support.duocircle.com/support/solutions/articles/5000540958-duocircle-standard-smtp-abuse-information X-Originating-IP: 73.78.92.27 X-Mail-Handler: DuoCircle Outbound SMTP Received: from ilsoft.org (unknown [73.78.92.27]) by outbound2.ore.mailhop.org (Halon) with ESMTPSA id 719ffe91-7639-11e7-a4a1-c9e62e5d9688; Mon, 31 Jul 2017 21:44:35 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.15.2/8.15.2) with ESMTP id v6VLjBES002268; Mon, 31 Jul 2017 15:45:11 -0600 (MDT) (envelope-from ian@freebsd.org) Message-ID: <1501537511.90400.116.camel@freebsd.org> Subject: Re: Allwinner GPIO IRQ? From: Ian Lepore To: Dustin Marquess , freebsd-arm@freebsd.org Date: Mon, 31 Jul 2017 15:45:11 -0600 In-Reply-To: References: Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.18.5.1 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Jul 2017 21:46:21 -0000 On Mon, 2017-07-31 at 15:38 -0500, Dustin Marquess wrote: > I'm trying to setup gpiopps on my Pine A64.  I managed to hack up the > device tree and that part seems to work, however I was getting: > > gpiopps0: Pin cannot be configured for the requested signal edge > > I noticed that sys/arm/allwinner/a10_gpio.c had: > > #define A10_GPIO_DEFAULT_CAPS   (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT > |     \ >     GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) > > So I changed that to: > > #define A10_GPIO_DEFAULT_CAPS   (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT > |     \ >     GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_MASK) > > That changed the error to: > > gpiopps0: Cannot allocate an IRQ for the GPIO > > And now I'm having problems finding a DEVMETHOD mapping for > bus_alloc_resource for the Allwinner gpios.  Am I right in guessing > that this code simply doesn't exist yet? > > Thanks! > -Dustin It looks like you've got the right bottom line: aw gpio isn't ready to support interrupts yet.  It's not because bus_alloc_resource is missing, it's because the code just doesn't support being an interrupt controller yet.  The methods missing are these (from imx_gpio.c): DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), DEVMETHOD(pic_map_intr, gpio_pic_map_intr), DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr), DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr), DEVMETHOD(pic_post_filter, gpio_pic_post_filter), DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), >From a quick glance at the docs, it looks like only 32 of the pins on allwinner can be configured as interrupt sources, but it doesn't look like our code is ready to do that at all (I don't see any pins in the padconf tables that have "irq" as one of their choices). -- Ian