From nobody Thu Dec 9 01:37:59 2021 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 87DE218D2D09; Thu, 9 Dec 2021 01:37:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4J8c9g1vHDz3Lb8; Thu, 9 Dec 2021 01:37:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 21A5B1E08B; Thu, 9 Dec 2021 01:37:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 1B91bxAg059491; Thu, 9 Dec 2021 01:37:59 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 1B91bx1X059490; Thu, 9 Dec 2021 01:37:59 GMT (envelope-from git) Date: Thu, 9 Dec 2021 01:37:59 GMT Message-Id: <202112090137.1B91bx1X059490@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Alexander Motin Subject: git: fd55c05ef706 - stable/12 - ig4: Add PCI IDs for Intel Alder Lake I2C controller. List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mav X-Git-Repository: src X-Git-Refname: refs/heads/stable/12 X-Git-Reftype: branch X-Git-Commit: fd55c05ef706b8fbbbacc1c6325a8f73b62c5d00 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1639013879; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=4p6vpCUq17YZH3K7lfZqX/jEIB8L1o5SvY/uNcKKeOw=; b=ryCqlJvwxrMa3SjtNf21stQLlTuqiKMZxY2+9q4A4w6ks6FJqbV0BpwZXDum4oGVM9Zl4F AjMB6gF052R9ZEMLofoe7lcMJf6Ymy6mID8v+fQBu1/vrQSDqHOCsmiatmUcXELzVykomp eAJz1wvr7nyTpLI4ao7kkHnM28bkCreZwZbjCC13C0GBHc27EkHwGbQLq0uKnOI4WW68xJ HOIzKqr0WyemWhPU7Iq26w3GbNcVZrMnYFcLJ9Vc3ef9ED2vKdp83CxBnZFOG+TxW6rI81 jkJb1UYgiTfeMvR8LuB+lcGfnmdRn+zpTBXsAkuh0C35HpdstvwF+ZzbLcNdGg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1639013879; a=rsa-sha256; cv=none; b=XbZxqUOpPb7F18jG+XtZ8hV/XfZv9IoanpTXzO1zSS2wEI1jSC6AkyW7O9GZ0pNO22fc5A WKSmf0hwLYL963T8h6BFCQLZVsj7ihB6TWgU5JsWDDhgb9LkLbL/id0kPaODVE5ZRo94yR JqFr5LyONJ+fMZ44mDxkEnJwUKVMAqSsovZIDcxAY+7Gm0BbznV6ECSZeXIxHa/xc5h/DB 1BgUnQWPpSXqTMHo6qpQ65va1IiDAOd4qgdD40cNgG1YUvKFW98GRzntFvfXFshUtxApba BICUqWq1aJ+rXxF4S6OOR9ERq2qBvlOZ9CSlfJedrO4iWZsrQA5ZguYgeLNd8A== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch stable/12 has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=fd55c05ef706b8fbbbacc1c6325a8f73b62c5d00 commit fd55c05ef706b8fbbbacc1c6325a8f73b62c5d00 Author: Alexander Motin AuthorDate: 2021-11-25 01:13:38 +0000 Commit: Alexander Motin CommitDate: 2021-12-09 01:37:53 +0000 ig4: Add PCI IDs for Intel Alder Lake I2C controller. Submitted by: Dmitry Luhtionov MFC after: 2 weeks (cherry picked from commit e8e8d2290ee68ddf8753ea345d4424f959bdb69d) --- sys/dev/ichiic/ig4_pci.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c index 2d80a8b1800a..71b95c3d95fb 100644 --- a/sys/dev/ichiic/ig4_pci.c +++ b/sys/dev/ichiic/ig4_pci.c @@ -144,6 +144,26 @@ static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_GEMINILAKE_I2C_5 0x31b68086 #define PCI_CHIP_GEMINILAKE_I2C_6 0x31b88086 #define PCI_CHIP_GEMINILAKE_I2C_7 0x31ba8086 +#define PCI_CHIP_ALDERLAKE_P_I2C_0 0x51e88086 +#define PCI_CHIP_ALDERLAKE_P_I2C_1 0x51e98086 +#define PCI_CHIP_ALDERLAKE_P_I2C_2 0x51ea8086 +#define PCI_CHIP_ALDERLAKE_P_I2C_3 0x51eb8086 +#define PCI_CHIP_ALDERLAKE_P_I2C_4 0x51c58086 +#define PCI_CHIP_ALDERLAKE_P_I2C_5 0x51c68086 +#define PCI_CHIP_ALDERLAKE_P_I2C_6 0x51d88086 +#define PCI_CHIP_ALDERLAKE_P_I2C_7 0x51d98086 +#define PCI_CHIP_ALDERLAKE_S_I2C_0 0x7acc8086 +#define PCI_CHIP_ALDERLAKE_S_I2C_1 0x7acd8086 +#define PCI_CHIP_ALDERLAKE_S_I2C_2 0x7ace8086 +#define PCI_CHIP_ALDERLAKE_S_I2C_3 0x7acf8086 +#define PCI_CHIP_ALDERLAKE_S_I2C_4 0x7afc8086 +#define PCI_CHIP_ALDERLAKE_S_I2C_5 0x7afd8086 +#define PCI_CHIP_ALDERLAKE_M_I2C_0 0x54e88086 +#define PCI_CHIP_ALDERLAKE_M_I2C_1 0x54e98086 +#define PCI_CHIP_ALDERLAKE_M_I2C_2 0x54ea8086 +#define PCI_CHIP_ALDERLAKE_M_I2C_3 0x54eb8086 +#define PCI_CHIP_ALDERLAKE_M_I2C_4 0x54c58086 +#define PCI_CHIP_ALDERLAKE_M_I2C_5 0x54c68086 struct ig4iic_pci_device { uint32_t devid; @@ -230,6 +250,26 @@ static struct ig4iic_pci_device ig4iic_pci_devices[] = { { PCI_CHIP_GEMINILAKE_I2C_5, "Intel Gemini Lake I2C Controller-5", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_6, "Intel Gemini Lake I2C Controller-6", IG4_GEMINILAKE}, { PCI_CHIP_GEMINILAKE_I2C_7, "Intel Gemini Lake I2C Controller-7", IG4_GEMINILAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_0, "Intel Alder Lake-P I2C Controller-0", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_1, "Intel Alder Lake-P I2C Controller-1", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_2, "Intel Alder Lake-P I2C Controller-2", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_3, "Intel Alder Lake-P I2C Controller-3", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_4, "Intel Alder Lake-P I2C Controller-4", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_5, "Intel Alder Lake-P I2C Controller-5", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_6, "Intel Alder Lake-P I2C Controller-6", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_P_I2C_7, "Intel Alder Lake-P I2C Controller-7", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_S_I2C_0, "Intel Alder Lake-S I2C Controller-0", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_S_I2C_1, "Intel Alder Lake-S I2C Controller-1", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_S_I2C_2, "Intel Alder Lake-S I2C Controller-2", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_S_I2C_3, "Intel Alder Lake-S I2C Controller-3", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_S_I2C_4, "Intel Alder Lake-S I2C Controller-4", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_S_I2C_5, "Intel Alder Lake-S I2C Controller-5", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_M_I2C_0, "Intel Alder Lake-M I2C Controller-0", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_M_I2C_1, "Intel Alder Lake-M I2C Controller-1", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_M_I2C_2, "Intel Alder Lake-M I2C Controller-2", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4", IG4_TIGERLAKE}, + { PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5", IG4_TIGERLAKE}, }; static int