From owner-freebsd-current Fri Jan 2 11:17:13 1998 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id LAA25111 for current-outgoing; Fri, 2 Jan 1998 11:17:13 -0800 (PST) (envelope-from owner-freebsd-current) Received: from flea.best.net (root@flea.best.net [206.184.139.131]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id LAA25085; Fri, 2 Jan 1998 11:16:57 -0800 (PST) (envelope-from dillon@flea.best.net) Received: (from dillon@localhost) by flea.best.net (8.8.8/8.7.3) id LAA14499; Fri, 2 Jan 1998 11:16:33 -0800 (PST) Date: Fri, 2 Jan 1998 11:16:33 -0800 (PST) From: Matt Dillon Message-Id: <199801021916.LAA14499@flea.best.net> To: "John S. Dyson" Cc: current@freebsd.org, dg@root.com Subject: Interesting page table methodology Sender: owner-freebsd-current@freebsd.org X-Loop: FreeBSD.org Precedence: bulk I've recently been studying the MMU on the PowerPC and MIPS cpus. The PowerPC's methodology in particular appeals to me. It's probably not possible to do something similar with the Pentium's hardwired MMU, but here is the basic idea. With the PowerPC & MIPS cpus you can take an interrupt on a TLB miss (on the MIPS you don't have a choice. On the PowerPC it's possible to do it either way depending on the chip0. The interrupt routine nominally obtains the TLB