From owner-svn-src-all@freebsd.org Fri Apr 22 21:32:25 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8F164B1881F; Fri, 22 Apr 2016 21:32:25 +0000 (UTC) (envelope-from zec@fer.hr) Received: from mail.fer.hr (mail.fer.hr [161.53.72.233]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mail.fer.hr", Issuer "TERENA SSL CA 3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 23F7919D1; Fri, 22 Apr 2016 21:32:24 +0000 (UTC) (envelope-from zec@fer.hr) Received: from x23 (31.147.120.67) by MAIL.fer.hr (161.53.72.233) with Microsoft SMTP Server (TLS) id 14.3.279.2; Fri, 22 Apr 2016 23:31:09 +0200 Date: Fri, 22 Apr 2016 23:31:37 +0200 From: Marko Zec To: Ruslan Bukin CC: , , Subject: Re: svn commit: r298477 - in head/sys: conf riscv/riscv Message-ID: <20160422233137.7f37bb47@x23> In-Reply-To: <201604221615.u3MGFxCM088374@repo.freebsd.org> References: <201604221615.u3MGFxCM088374@repo.freebsd.org> X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.29; amd64-portbld-freebsd10.1) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [31.147.120.67] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Apr 2016 21:32:25 -0000 On Fri, 22 Apr 2016 16:15:59 +0000 Ruslan Bukin wrote: > Author: br > Date: Fri Apr 22 16:15:58 2016 > New Revision: 298477 > URL: https://svnweb.freebsd.org/changeset/base/298477 > > Log: > Clear the DDR memory. This should be done by bootloaders, > but they have no such feature yet. > > This fixes operation on Rocket Core and lowRISC. > > Modified: > head/sys/conf/options.riscv > head/sys/riscv/riscv/locore.S > > Modified: head/sys/conf/options.riscv > ============================================================================== > --- head/sys/conf/options.riscv Fri Apr 22 15:12:05 > 2016 (r298476) +++ head/sys/conf/options.riscv Fri Apr > 22 16:15:58 2016 (r298477) @@ -2,3 +2,4 @@ > > RISCV opt_global.h > VFP opt_global.h > +DDR_CLEAR_SIZE opt_global.h > > Modified: head/sys/riscv/riscv/locore.S > ============================================================================== > --- head/sys/riscv/riscv/locore.S Fri Apr 22 15:12:05 > 2016 (r298476) +++ head/sys/riscv/riscv/locore.S Fri > Apr 22 16:15:58 2016 (r298477) @@ -126,6 +126,17 @@ _start: > csrr a0, mhartid > bnez a0, mpentry > > +#if defined(DDR_CLEAR_SIZE) > + /* Clear DDR memory */ > + la t0, _end > + li t1, DDR_CLEAR_SIZE > +1: > + sd zero, 0(t0) > + addi t0, t0, 8 > + bltu t0, t1, 1b Usually _end appears to be (double) word aligned, but that happens out of pure luck, since compilers do not provide firm guarantees about _end's alignment (at least gcc doesn't, as far as I know). So depending on which kind of RV this code would run, sometimes it may end up doing a lot of traps emulating unaligned access in software, or worse... Hence it would't hurt to check for _end's alignment first and do a few byte-by-byte bzero()ing if needed, before proceeding a dword pace. > + /* End */ > +#endif > + > /* Build event queue for current core */ > build_ring > >