Date: Sun, 4 Jul 1999 17:03:58 -0400 (EDT) From: Louis Mamakos <louie@TransSys.COM> To: FreeBSD-gnats-submit@freebsd.org Subject: kern/12512: additional support for K6-III CPU information messages Message-ID: <199907042103.RAA00630@whizzo.transsys.com>
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>Number: 12512
>Category: kern
>Synopsis: additional support for K6-III CPU information messages
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-bugs
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: sw-bug
>Submitter-Id: current-users
>Arrival-Date: Sun Jul 4 14:10:00 PDT 1999
>Closed-Date:
>Last-Modified:
>Originator: Louis Mamakos
>Release: FreeBSD 4.0-CURRENT i386
>Organization:
>Environment:
K6-III CPU
>Description:
Wonder if they *really* sold you a K6-III CPU, and not some
other weird thing?
Add support to print_AMD_info to display L2 cache information
for AMD K6-III CPU. Additionally, display K6-model-specific
capabilities.
>How-To-Repeat:
dmesg now produces
CPU: AMD-K6(tm) 3D+ Processor (450.92-MHz 586-class CPU)
Origin = "AuthenticAMD" Id = 0x591 Stepping=1
Features=0x8021bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,PGE,MMX>
AMD Extended Features=0x808029bf<FPU,VME,DE,PSE,TSC,K6MSR,MCE,CX8,SYSCALL,PGE,MMX,3DNow!>
Data TLB: 128 entries, 2-way associative
Instruction TLB: 64 entries, 1-way associative
L1 data cache: 32 kbytes, 32 bytes/line, 2 lines/tag, 2-way associative
L1 instruction cache: 32 kbytes, 32 bytes/line, 2 lines/tag, 2-way associative
L2 (on-CPU) cache: 256 kbytes, 32 bytes/line, 2 lines/tag, 4-way associative
Write Allocate Enable Limit: 128M bytes
Write Allocate 15-16M bytes: Enable
>Fix:
Index: sys/i386/i386/identcpu.c
===================================================================
RCS file: /usr/local/FreeBSD/cvs/src/sys/i386/i386/identcpu.c,v
retrieving revision 1.65
diff -u -r1.65 identcpu.c
--- identcpu.c 1999/06/24 20:08:56 1.65
+++ identcpu.c 1999/07/04 20:51:54
@@ -295,6 +295,9 @@
case 0x580:
strcat(cpu_model, "K6-2");
break;
+ case 0x590:
+ strcat(cpu_model, "K6-III");
+ break;
default:
strcat(cpu_model, "Unknown");
break;
@@ -866,11 +869,52 @@
static void
print_AMD_info(void)
{
- u_int regs[4];
+ u_int regs[4], amd_maxregs;
quad_t amd_whcr;
do_cpuid(0x80000000, regs);
- if (regs[0] >= 0x80000005) {
+ amd_maxregs = regs[0];
+
+ if (amd_maxregs >= 0x80000001) {
+ do_cpuid(0x80000001, regs);
+ printf("AMD Extended Features=0x%b\n", regs[3],
+ "\020" /* in hex */
+ "\001FPU"
+ "\002VME"
+ "\003DE"
+ "\004PSE"
+ "\005TSC"
+ "\006K6MSR"
+ "\007b6"
+ "\010MCE"
+ "\011CX8"
+ "\012b9"
+ "\013b10"
+ "\014SYSCALL"
+ "\015b12"
+ "\016PGE"
+ "\017b14"
+ "\020ICMOV"
+ "\021FCMOV"
+ "\022b17"
+ "\023b18"
+ "\024b19"
+ "\025b20"
+ "\026b21"
+ "\027b22"
+ "\030MMX"
+ "\031b24"
+ "\032b25"
+ "\033b26"
+ "\034b27"
+ "\035b28"
+ "\036b29"
+ "\037b30"
+ "\0403DNow!"
+ );
+ }
+
+ if (amd_maxregs >= 0x80000005) {
do_cpuid(0x80000005, regs);
printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
print_AMD_assoc(regs[1] >> 24);
@@ -884,6 +928,15 @@
printf(", %d bytes/line", regs[3] & 0xff);
printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
print_AMD_assoc((regs[3] >> 16) & 0xff);
+
+ /* check for K6-III on-board L2 cache */
+ if (amd_maxregs >= 0x80000006) {
+ do_cpuid(0x80000006, regs);
+ printf("L2 (on-CPU) cache: %d kbytes", regs[2] >> 16);
+ printf(", %d bytes/line", regs[2] & 0xff);
+ printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
+ print_AMD_assoc((regs[2] >> 12) & 0x0f);
+ }
}
if (((cpu_id & 0xf00) == 0x500)
&& (((cpu_id & 0x0f0) > 0x80)
>Release-Note:
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