From owner-svn-src-all@freebsd.org Fri May 10 16:45:18 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 9670215A7343; Fri, 10 May 2019 16:45:18 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 3D68880EF5; Fri, 10 May 2019 16:45:18 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 1A9FD6FDA; Fri, 10 May 2019 16:45:18 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x4AGjHeV088152; Fri, 10 May 2019 16:45:17 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x4AGjH6R088150; Fri, 10 May 2019 16:45:17 GMT (envelope-from manu@FreeBSD.org) Message-Id: <201905101645.x4AGjH6R088150@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Fri, 10 May 2019 16:45:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r347442 - head/sys/arm64/rockchip/clk X-SVN-Group: head X-SVN-Commit-Author: manu X-SVN-Commit-Paths: head/sys/arm64/rockchip/clk X-SVN-Commit-Revision: 347442 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 3D68880EF5 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.97 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.995,0]; NEURAL_HAM_SHORT(-0.98)[-0.978,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 May 2019 16:45:18 -0000 Author: manu Date: Fri May 10 16:45:17 2019 New Revision: 347442 URL: https://svnweb.freebsd.org/changeset/base/347442 Log: arm64: rockchip: Don't always put PLL to normal mode We used to put every PLL in normal mode (meaning that the output would be the result of the PLL configuration) instead of slow mode (the output is equal to the external oscillator frequency, 24-26Mhz) but this doesn't work for most of the PLLs as when we put them into normal mode the registers configuring the output frequency haven't been set. Add a normal_mode member in clk_pll_def/clk_pll_sc struct and if it's true we then set the PLL to normal mode. For now only set it to the LPLL and BPLL (Little cluster PLL and Big cluster PLL respectively). Reviewed by: ganbold Differential Revision: https://reviews.freebsd.org/D20174 Modified: head/sys/arm64/rockchip/clk/rk3399_cru.c head/sys/arm64/rockchip/clk/rk_clk_pll.c head/sys/arm64/rockchip/clk/rk_clk_pll.h Modified: head/sys/arm64/rockchip/clk/rk3399_cru.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk3399_cru.c Fri May 10 16:44:35 2019 (r347441) +++ head/sys/arm64/rockchip/clk/rk3399_cru.c Fri May 10 16:45:17 2019 (r347442) @@ -764,6 +764,7 @@ static struct rk_clk_pll_def lpll = { .gate_shift = 0, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, + .normal_mode = true, }; static struct rk_clk_pll_def bpll = { @@ -778,6 +779,7 @@ static struct rk_clk_pll_def bpll = { .gate_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, + .normal_mode = true, }; static struct rk_clk_pll_def dpll = { Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.c Fri May 10 16:44:35 2019 (r347441) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.c Fri May 10 16:45:17 2019 (r347442) @@ -54,6 +54,8 @@ struct rk_clk_pll_sc { struct rk_clk_pll_rate *rates; struct rk_clk_pll_rate *frac_rates; + + bool normal_mode; }; #define WRITE4(_clk, off, val) \ @@ -344,11 +346,13 @@ rk3399_clk_pll_init(struct clknode *clk, device_t dev) sc = clknode_get_softc(clk); - /* Setting to normal mode */ - reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; - reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; - WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET, - reg | RK3399_CLK_PLL_WRITE_MASK); + if (sc->normal_mode) { + /* Setting to normal mode */ + reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; + reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; + WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET, + reg | RK3399_CLK_PLL_WRITE_MASK); + } clknode_init_parent_idx(clk, 0); @@ -521,6 +525,7 @@ rk3399_clk_pll_register(struct clkdom *clkdom, struct sc->flags = clkdef->flags; sc->rates = clkdef->rates; sc->frac_rates = clkdef->frac_rates; + sc->normal_mode = clkdef->normal_mode; clknode_register(clkdom, clk); Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.h ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.h Fri May 10 16:44:35 2019 (r347441) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.h Fri May 10 16:45:17 2019 (r347442) @@ -57,6 +57,8 @@ struct rk_clk_pll_def { struct rk_clk_pll_rate *rates; struct rk_clk_pll_rate *frac_rates; + + bool normal_mode; }; #define RK_CLK_PLL_HAVE_GATE 0x1