From owner-freebsd-hackers@FreeBSD.ORG Thu Mar 6 13:33:56 2008 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 89A941065675 for ; Thu, 6 Mar 2008 13:33:56 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from elvis.mu.org (elvis.mu.org [192.203.228.196]) by mx1.freebsd.org (Postfix) with ESMTP id 780908FC22 for ; Thu, 6 Mar 2008 13:33:56 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from zion.baldwin.cx (66-23-211-162.clients.speedfactory.net [66.23.211.162]) by elvis.mu.org (Postfix) with ESMTP id EEE721A4D7C; Thu, 6 Mar 2008 05:33:30 -0800 (PST) From: John Baldwin To: freebsd-hackers@freebsd.org Date: Thu, 6 Mar 2008 07:52:27 -0500 User-Agent: KMail/1.9.7 References: <47B4A514.1020103@icyb.net.ua> <47B8055C.4060305@icyb.net.ua> In-Reply-To: <47B8055C.4060305@icyb.net.ua> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200803060752.27235.jhb@freebsd.org> Cc: Andriy Gapon Subject: Re: cpu stats and another interrupt question X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Mar 2008 13:33:56 -0000 On Sunday 17 February 2008 04:58:52 am Andriy Gapon wrote: > Come on, guys, simple yes or no would be enough for me :-) > > on 14/02/2008 22:31 Andriy Gapon said the following: > > Dear hackers, > > I'd like to check with you if my understanding of some code is correct. > > > > If we speak about a typical older i386 system, with UP and "AT" PIC, I > > think this is how the CPU utilization stats are collected. > > RTC is configured to generate interrupts (IRQ8) 128 times per second. > > Each time interrupt is generated RTC interrupt handler (I will use > > simple non technical terms) takes a peek at what was interrupted and > > depending on the properties of that thing (kernel thread) bills a tick > > to particular category. E.g. if it sees that the "idle" thread is > > interrupted then a tick is billed to "idle", if an interrupt thread is > > interrupted (software or hardware) then a tick is billed to interrupt, > > if a thread is running user-mode code then a tick is billed to "user" or > > "nice", otherwise it's "system". > > I understand that I oversimplify, but is the above correct in general ? > > > > Another, unrelated, question. > > Considering this snippet from sys/i386/isa/atpic.c, i8259_init(): > > #ifndef PC98 > > /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */ > > if (!slave) > > outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1); > > #endif > > > > Do I understand correctly the code and the comment that here we use a > > feature of 8259 PIC that can be called "cyclic shift of interrupt > > priorities" ? > > So, we really have the following order of interrupts, from higher > > priority to lower: 3-7,0,1,8-15? Considering two chained 8259s, of > > course. Yes and yes. -- John Baldwin