From owner-svn-src-all@freebsd.org Sat Feb 4 19:35:40 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 09570CD104C; Sat, 4 Feb 2017 19:35:40 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B4D961F30; Sat, 4 Feb 2017 19:35:39 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v14JZcmK045952; Sat, 4 Feb 2017 19:35:38 GMT (envelope-from marius@FreeBSD.org) Received: (from marius@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v14JZc2U045946; Sat, 4 Feb 2017 19:35:38 GMT (envelope-from marius@FreeBSD.org) Message-Id: <201702041935.v14JZc2U045946@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: marius set sender to marius@FreeBSD.org using -f From: Marius Strobl Date: Sat, 4 Feb 2017 19:35:38 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r313250 - in head/sys/dev: mmc sdhci X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 Feb 2017 19:35:40 -0000 Author: marius Date: Sat Feb 4 19:35:38 2017 New Revision: 313250 URL: https://svnweb.freebsd.org/changeset/base/313250 Log: Fix some more overly long lines, whitespace and other bugs according to style(9) as well as spelling in comments. Modified: head/sys/dev/mmc/mmc.c head/sys/dev/mmc/mmcreg.h head/sys/dev/sdhci/sdhci.c head/sys/dev/sdhci/sdhci.h head/sys/dev/sdhci/sdhci_fdt.c head/sys/dev/sdhci/sdhci_pci.c Modified: head/sys/dev/mmc/mmc.c ============================================================================== --- head/sys/dev/mmc/mmc.c Sat Feb 4 19:16:19 2017 (r313249) +++ head/sys/dev/mmc/mmc.c Sat Feb 4 19:35:38 2017 (r313250) @@ -111,14 +111,15 @@ struct mmc_ivars { char card_sn_string[16];/* Formatted serial # for disk->d_ident */ }; -#define CMD_RETRIES 3 +#define CMD_RETRIES 3 #define CARD_ID_FREQUENCY 400000 /* Spec requires 400kHz max during ID phase. */ static SYSCTL_NODE(_hw, OID_AUTO, mmc, CTLFLAG_RD, NULL, "mmc driver"); static int mmc_debug; -SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &mmc_debug, 0, "Debug level"); +SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &mmc_debug, 0, + "Debug level"); /* bus entry points */ static int mmc_acquire_bus(device_t busdev, device_t dev); @@ -137,14 +138,14 @@ static int mmc_wait_for_request(device_t static int mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value); -#define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) -#define MMC_LOCK_INIT(_sc) \ - mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ +#define MMC_LOCK_INIT(_sc) \ + mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->dev), \ "mmc", MTX_DEF) -#define MMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); -#define MMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); -#define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); +#define MMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); +#define MMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED); +#define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED); static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid); static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr); @@ -744,9 +745,9 @@ mmc_set_card_bus_width(struct mmc_softc static int mmc_set_timing(struct mmc_softc *sc, int timing) { + u_char switch_res[64]; int err; uint8_t value; - u_char switch_res[64]; switch (timing) { case bus_timing_normal: @@ -1161,9 +1162,9 @@ mmc_app_send_scr(struct mmc_softc *sc, u static int mmc_send_ext_csd(struct mmc_softc *sc, uint8_t *rawextcsd) { - int err; struct mmc_command cmd; struct mmc_data data; + int err; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); @@ -1185,9 +1186,9 @@ mmc_send_ext_csd(struct mmc_softc *sc, u static int mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus) { - int err, i; struct mmc_command cmd; struct mmc_data data; + int err, i; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); @@ -1393,7 +1394,7 @@ mmc_discover_cards(struct mmc_softc *sc) * commands, although the state tables / diagrams in the * standard suggest they go back to the transfer state. * Other cards don't become deselected, and if we - * atttempt to blindly re-select them, we get timeout + * attempt to blindly re-select them, we get timeout * errors from some controllers. So we deselect then * reselect to handle all situations. The only thing we * use from the sd_status is the erase sector size, but @@ -1534,7 +1535,7 @@ mmc_discover_cards(struct mmc_softc *sc) static void mmc_rescan_cards(struct mmc_softc *sc) { - struct mmc_ivars *ivar = NULL; + struct mmc_ivars *ivar; device_t *devlist; int err, i, devcount; @@ -1664,14 +1665,13 @@ mmc_go_discovery(struct mmc_softc *sc) static int mmc_calculate_clock(struct mmc_softc *sc) { - int max_dtr, max_hs_dtr, max_timing; - int nkid, i, f_max; device_t *kids; struct mmc_ivars *ivar; + int i, f_max, max_dtr, max_hs_dtr, max_timing, nkid; f_max = mmcbr_get_f_max(sc->dev); max_dtr = max_hs_dtr = f_max; - if ((mmcbr_get_caps(sc->dev) & MMC_CAP_HSPEED)) + if (mmcbr_get_caps(sc->dev) & MMC_CAP_HSPEED) max_timing = bus_timing_hs; else max_timing = bus_timing_normal; Modified: head/sys/dev/mmc/mmcreg.h ============================================================================== --- head/sys/dev/mmc/mmcreg.h Sat Feb 4 19:16:19 2017 (r313249) +++ head/sys/dev/mmc/mmcreg.h Sat Feb 4 19:35:38 2017 (r313250) @@ -100,7 +100,7 @@ struct mmc_command { #define MMC_ERR_FAILED 4 #define MMC_ERR_INVALID 5 #define MMC_ERR_NO_MEMORY 6 -#define MMC_ERR_MAX 6 +#define MMC_ERR_MAX 6 struct mmc_data *data; /* Data segment with cmd */ struct mmc_request *mrq; /* backpointer to request */ }; @@ -291,47 +291,47 @@ struct mmc_request { /* * EXT_CSD fields */ -#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */ -#define EXT_CSD_BUS_WIDTH 183 /* R/W */ -#define EXT_CSD_HS_TIMING 185 /* R/W */ -#define EXT_CSD_CARD_TYPE 196 /* RO */ -#define EXT_CSD_REV 192 /* RO */ -#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ -#define EXT_CSD_ERASE_TO_MULT 223 /* RO */ -#define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_ERASE_TO_MULT 223 /* RO */ +#define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */ /* * EXT_CSD field definitions */ -#define EXT_CSD_CMD_SET_NORMAL 1 -#define EXT_CSD_CMD_SET_SECURE 2 -#define EXT_CSD_CMD_SET_CPSECURE 4 - -#define EXT_CSD_CARD_TYPE_26 1 -#define EXT_CSD_CARD_TYPE_52 2 - -#define EXT_CSD_BUS_WIDTH_1 0 -#define EXT_CSD_BUS_WIDTH_4 1 -#define EXT_CSD_BUS_WIDTH_8 2 +#define EXT_CSD_CMD_SET_NORMAL 1 +#define EXT_CSD_CMD_SET_SECURE 2 +#define EXT_CSD_CMD_SET_CPSECURE 4 + +#define EXT_CSD_CARD_TYPE_26 1 +#define EXT_CSD_CARD_TYPE_52 2 + +#define EXT_CSD_BUS_WIDTH_1 0 +#define EXT_CSD_BUS_WIDTH_4 1 +#define EXT_CSD_BUS_WIDTH_8 2 -#define MMC_TYPE_26_MAX_HS 26000000 -#define MMC_TYPE_52_MAX_HS 52000000 +#define MMC_TYPE_26_MAX_HS 26000000 +#define MMC_TYPE_52_MAX_HS 52000000 /* * SD bus widths */ -#define SD_BUS_WIDTH_1 0 -#define SD_BUS_WIDTH_4 2 +#define SD_BUS_WIDTH_1 0 +#define SD_BUS_WIDTH_4 2 /* * SD Switch */ -#define SD_SWITCH_MODE_CHECK 0 -#define SD_SWITCH_MODE_SET 1 -#define SD_SWITCH_GROUP1 0 -#define SD_SWITCH_NORMAL_MODE 0 -#define SD_SWITCH_HS_MODE 1 -#define SD_SWITCH_NOCHANGE 0xF +#define SD_SWITCH_MODE_CHECK 0 +#define SD_SWITCH_MODE_SET 1 +#define SD_SWITCH_GROUP1 0 +#define SD_SWITCH_NORMAL_MODE 0 +#define SD_SWITCH_HS_MODE 1 +#define SD_SWITCH_NOCHANGE 0xF #define SD_CLR_CARD_DETECT 0 #define SD_SET_CARD_DETECT 1 @@ -419,8 +419,8 @@ struct mmc_scr { unsigned char sda_vsn; unsigned char bus_widths; -#define SD_SCR_BUS_WIDTH_1 (1<<0) -#define SD_SCR_BUS_WIDTH_4 (1<<2) +#define SD_SCR_BUS_WIDTH_1 (1 << 0) +#define SD_SCR_BUS_WIDTH_4 (1 << 2) }; struct mmc_sd_status @@ -443,6 +443,6 @@ struct mmc_sd_status * byte sector size anywhere, so we assume that such cards are very rare * and only note their existence in passing here... */ -#define MMC_SECTOR_SIZE 512 +#define MMC_SECTOR_SIZE 512 #endif /* DEV_MMCREG_H */ Modified: head/sys/dev/sdhci/sdhci.c ============================================================================== --- head/sys/dev/sdhci/sdhci.c Sat Feb 4 19:16:19 2017 (r313249) +++ head/sys/dev/sdhci/sdhci.c Sat Feb 4 19:35:38 2017 (r313250) @@ -55,18 +55,19 @@ __FBSDID("$FreeBSD$"); SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); static int sdhci_debug; -SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level"); +SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, + "Debug level"); -#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) -#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) -#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) -#define RD_MULTI_4(slot, off, ptr, count) \ +#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) +#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) +#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) +#define RD_MULTI_4(slot, off, ptr, count) \ SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) -#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) -#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) -#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) -#define WR_MULTI_4(slot, off, ptr, count) \ +#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) +#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) +#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) +#define WR_MULTI_4(slot, off, ptr, count) \ SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); @@ -77,13 +78,13 @@ static void sdhci_card_poll(void *); static void sdhci_card_task(void *, int); /* helper routines */ -#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) +#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) -#define SDHCI_LOCK_INIT(_slot) \ +#define SDHCI_LOCK_INIT(_slot) \ mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) -#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); -#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); -#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); +#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); +#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); +#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); #define SDHCI_DEFAULT_MAX_FREQ 50 @@ -97,20 +98,20 @@ static void sdhci_card_task(void *, int) * Broadcom BCM577xx Controller Constants */ /* Maximum divider supported by the default clock source. */ -#define BCM577XX_DEFAULT_MAX_DIVIDER 256 +#define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Alternative clock's base frequency. */ -#define BCM577XX_ALT_CLOCK_BASE 63000000 - -#define BCM577XX_HOST_CONTROL 0x198 -#define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF -#define BCM577XX_CTRL_CLKSEL_SHIFT 12 -#define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 -#define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 +#define BCM577XX_ALT_CLOCK_BASE 63000000 +#define BCM577XX_HOST_CONTROL 0x198 +#define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF +#define BCM577XX_CTRL_CLKSEL_SHIFT 12 +#define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 +#define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { + if (error != 0) { printf("getaddr: error %d\n", error); return; @@ -136,6 +137,7 @@ slot_printf(struct sdhci_slot *slot, con static void sdhci_dumpregs(struct sdhci_slot *slot) { + slot_printf(slot, "============== REGISTER DUMP ==============\n"); @@ -498,9 +500,10 @@ sdhci_transfer_pio(struct sdhci_slot *sl } static void -sdhci_card_task(void *arg, int pending) +sdhci_card_task(void *arg, int pending __unused) { struct sdhci_slot *slot = arg; + device_t d; SDHCI_LOCK(slot); if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { @@ -519,7 +522,7 @@ sdhci_card_task(void *arg, int pending) /* If no card present - detach mmc bus. */ if (bootverbose || sdhci_debug) slot_printf(slot, "Card removed\n"); - device_t d = slot->dev; + d = slot->dev; slot->dev = NULL; SDHCI_UNLOCK(slot); device_delete_child(slot->bus, d); @@ -739,6 +742,7 @@ sdhci_init_slot(device_t dev, struct sdh void sdhci_start_slot(struct sdhci_slot *slot) { + sdhci_card_task(slot, 0); } @@ -774,6 +778,7 @@ sdhci_cleanup_slot(struct sdhci_slot *sl int sdhci_generic_suspend(struct sdhci_slot *slot) { + sdhci_reset(slot, SDHCI_RESET_ALL); return (0); @@ -782,6 +787,7 @@ sdhci_generic_suspend(struct sdhci_slot int sdhci_generic_resume(struct sdhci_slot *slot) { + sdhci_init(slot); return (0); @@ -790,6 +796,7 @@ sdhci_generic_resume(struct sdhci_slot * uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) { + if (slot->version >= SDHCI_SPEC_300) return (slot->max_clk / SDHCI_300_MAX_DIVIDER); else @@ -869,7 +876,7 @@ sdhci_timeout(void *arg) if (slot->curcmd != NULL) { slot_printf(slot, " Controller timeout\n"); sdhci_dumpregs(slot); - sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); + sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); slot->curcmd->error = MMC_ERR_TIMEOUT; sdhci_req_done(slot); } else { @@ -1122,6 +1129,7 @@ void sdhci_finish_data(struct sdhci_slot *slot) { struct mmc_data *data = slot->curcmd->data; + size_t left; /* Interrupt aggregation: Restore command interrupt. * Auxiliary restore point for the case when data interrupt @@ -1133,7 +1141,7 @@ sdhci_finish_data(struct sdhci_slot *slo /* Unload rest of data from DMA buffer. */ if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { if (data->flags & MMC_DATA_READ) { - size_t left = data->len - slot->offset; + left = data->len - slot->offset; bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); memcpy((u_char*)data->data + slot->offset, slot->dmamem, @@ -1433,7 +1441,7 @@ sdhci_generic_intr(struct sdhci_slot *sl /* Handle data interrupts. */ if (intmask & SDHCI_INT_DATA_MASK) { WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); - /* Dont call data_irq in case of errored command */ + /* Don't call data_irq in case of errored command. */ if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); } Modified: head/sys/dev/sdhci/sdhci.h ============================================================================== --- head/sys/dev/sdhci/sdhci.h Sat Feb 4 19:16:19 2017 (r313249) +++ head/sys/dev/sdhci/sdhci.h Sat Feb 4 19:35:38 2017 (r313250) @@ -28,246 +28,246 @@ #ifndef __SDHCI_H__ #define __SDHCI_H__ -#define DMA_BLOCK_SIZE 4096 -#define DMA_BOUNDARY 0 /* DMA reload every 4K */ +#define DMA_BLOCK_SIZE 4096 +#define DMA_BOUNDARY 0 /* DMA reload every 4K */ /* Controller doesn't honor resets unless we touch the clock register */ -#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) +#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) /* Controller really supports DMA */ -#define SDHCI_QUIRK_FORCE_DMA (1<<1) +#define SDHCI_QUIRK_FORCE_DMA (1 << 1) /* Controller has unusable DMA engine */ -#define SDHCI_QUIRK_BROKEN_DMA (1<<2) +#define SDHCI_QUIRK_BROKEN_DMA (1 << 2) /* Controller doesn't like to be reset when there is no card inserted. */ -#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) +#define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3) /* Controller has flaky internal state so reset it on each ios change */ -#define SDHCI_QUIRK_RESET_ON_IOS (1<<4) +#define SDHCI_QUIRK_RESET_ON_IOS (1 << 4) /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ -#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) +#define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5) /* Controller needs to be reset after each request to stay stable */ -#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) +#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6) /* Controller has an off-by-one issue with timeout value */ -#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) +#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7) /* Controller has broken read timings */ -#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) +#define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8) /* Controller needs lowered frequency */ -#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) +#define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9) /* Data timeout is invalid, should use SD clock */ -#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<10) +#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10) /* Timeout value is invalid, should be overriden */ -#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11) +#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11) /* SDHCI_CAPABILITIES is invalid */ -#define SDHCI_QUIRK_MISSING_CAPS (1<<12) +#define SDHCI_QUIRK_MISSING_CAPS (1 << 12) /* Hardware shifts the 136-bit response, don't do it in software. */ -#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) +#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13) /* Wait to see reset bit asserted before waiting for de-asserted */ -#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14) +#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14) /* Leave controller in standard mode when putting card in HS mode. */ -#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1<<15) +#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15) /* Alternate clock source is required when supplying a 400 KHz clock. */ -#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1<<16) +#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16) /* Card insert/remove interrupts don't work, polling required. */ -#define SDHCI_QUIRK_POLL_CARD_PRESENT (1<<17) +#define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17) /* All controller slots are non-removable. */ -#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1<<18) +#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18) /* Issue custom Intel controller reset sequence after power-up. */ -#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1<<19) +#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19) /* Data timeout is invalid, use 1 MHz clock instead. */ -#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1<<20) +#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20) /* * Controller registers */ -#define SDHCI_DMA_ADDRESS 0x00 +#define SDHCI_DMA_ADDRESS 0x00 -#define SDHCI_BLOCK_SIZE 0x04 -#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) -#define SDHCI_BLOCK_COUNT 0x06 +#define SDHCI_BLOCK_COUNT 0x06 -#define SDHCI_ARGUMENT 0x08 +#define SDHCI_ARGUMENT 0x08 -#define SDHCI_TRANSFER_MODE 0x0C -#define SDHCI_TRNS_DMA 0x01 -#define SDHCI_TRNS_BLK_CNT_EN 0x02 -#define SDHCI_TRNS_ACMD12 0x04 -#define SDHCI_TRNS_READ 0x10 -#define SDHCI_TRNS_MULTI 0x20 - -#define SDHCI_COMMAND_FLAGS 0x0E -#define SDHCI_CMD_RESP_NONE 0x00 -#define SDHCI_CMD_RESP_LONG 0x01 -#define SDHCI_CMD_RESP_SHORT 0x02 -#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 -#define SDHCI_CMD_RESP_MASK 0x03 -#define SDHCI_CMD_CRC 0x08 -#define SDHCI_CMD_INDEX 0x10 -#define SDHCI_CMD_DATA 0x20 -#define SDHCI_CMD_TYPE_NORMAL 0x00 -#define SDHCI_CMD_TYPE_SUSPEND 0x40 -#define SDHCI_CMD_TYPE_RESUME 0x80 -#define SDHCI_CMD_TYPE_ABORT 0xc0 -#define SDHCI_CMD_TYPE_MASK 0xc0 - -#define SDHCI_COMMAND 0x0F - -#define SDHCI_RESPONSE 0x10 - -#define SDHCI_BUFFER 0x20 - -#define SDHCI_PRESENT_STATE 0x24 -#define SDHCI_CMD_INHIBIT 0x00000001 -#define SDHCI_DAT_INHIBIT 0x00000002 -#define SDHCI_DAT_ACTIVE 0x00000004 -#define SDHCI_RETUNE_REQUEST 0x00000008 -#define SDHCI_DOING_WRITE 0x00000100 -#define SDHCI_DOING_READ 0x00000200 -#define SDHCI_SPACE_AVAILABLE 0x00000400 -#define SDHCI_DATA_AVAILABLE 0x00000800 -#define SDHCI_CARD_PRESENT 0x00010000 -#define SDHCI_CARD_STABLE 0x00020000 -#define SDHCI_CARD_PIN 0x00040000 -#define SDHCI_WRITE_PROTECT 0x00080000 -#define SDHCI_STATE_DAT_MASK 0x00f00000 -#define SDHCI_STATE_CMD 0x01000000 - -#define SDHCI_HOST_CONTROL 0x28 -#define SDHCI_CTRL_LED 0x01 -#define SDHCI_CTRL_4BITBUS 0x02 -#define SDHCI_CTRL_HISPD 0x04 -#define SDHCI_CTRL_SDMA 0x08 -#define SDHCI_CTRL_ADMA2 0x10 -#define SDHCI_CTRL_ADMA264 0x18 -#define SDHCI_CTRL_DMA_MASK 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 -#define SDHCI_CTRL_CARD_DET 0x40 -#define SDHCI_CTRL_FORCE_CARD 0x80 - -#define SDHCI_POWER_CONTROL 0x29 -#define SDHCI_POWER_ON 0x01 -#define SDHCI_POWER_180 0x0A -#define SDHCI_POWER_300 0x0C -#define SDHCI_POWER_330 0x0E - -#define SDHCI_BLOCK_GAP_CONTROL 0x2A - -#define SDHCI_WAKE_UP_CONTROL 0x2B - -#define SDHCI_CLOCK_CONTROL 0x2C -#define SDHCI_DIVIDER_MASK 0xff -#define SDHCI_DIVIDER_MASK_LEN 8 -#define SDHCI_DIVIDER_SHIFT 8 -#define SDHCI_DIVIDER_HI_MASK 3 -#define SDHCI_DIVIDER_HI_SHIFT 6 -#define SDHCI_CLOCK_CARD_EN 0x0004 -#define SDHCI_CLOCK_INT_STABLE 0x0002 -#define SDHCI_CLOCK_INT_EN 0x0001 -#define SDHCI_DIVIDERS_MASK \ +#define SDHCI_TRANSFER_MODE 0x0C +#define SDHCI_TRNS_DMA 0x01 +#define SDHCI_TRNS_BLK_CNT_EN 0x02 +#define SDHCI_TRNS_ACMD12 0x04 +#define SDHCI_TRNS_READ 0x10 +#define SDHCI_TRNS_MULTI 0x20 + +#define SDHCI_COMMAND_FLAGS 0x0E +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 +#define SDHCI_CMD_TYPE_NORMAL 0x00 +#define SDHCI_CMD_TYPE_SUSPEND 0x40 +#define SDHCI_CMD_TYPE_RESUME 0x80 +#define SDHCI_CMD_TYPE_ABORT 0xc0 +#define SDHCI_CMD_TYPE_MASK 0xc0 + +#define SDHCI_COMMAND 0x0F + +#define SDHCI_RESPONSE 0x10 + +#define SDHCI_BUFFER 0x20 + +#define SDHCI_PRESENT_STATE 0x24 +#define SDHCI_CMD_INHIBIT 0x00000001 +#define SDHCI_DAT_INHIBIT 0x00000002 +#define SDHCI_DAT_ACTIVE 0x00000004 +#define SDHCI_RETUNE_REQUEST 0x00000008 +#define SDHCI_DOING_WRITE 0x00000100 +#define SDHCI_DOING_READ 0x00000200 +#define SDHCI_SPACE_AVAILABLE 0x00000400 +#define SDHCI_DATA_AVAILABLE 0x00000800 +#define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_STABLE 0x00020000 +#define SDHCI_CARD_PIN 0x00040000 +#define SDHCI_WRITE_PROTECT 0x00080000 +#define SDHCI_STATE_DAT_MASK 0x00f00000 +#define SDHCI_STATE_CMD 0x01000000 + +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_CTRL_LED 0x01 +#define SDHCI_CTRL_4BITBUS 0x02 +#define SDHCI_CTRL_HISPD 0x04 +#define SDHCI_CTRL_SDMA 0x08 +#define SDHCI_CTRL_ADMA2 0x10 +#define SDHCI_CTRL_ADMA264 0x18 +#define SDHCI_CTRL_DMA_MASK 0x18 +#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_CARD_DET 0x40 +#define SDHCI_CTRL_FORCE_CARD 0x80 + +#define SDHCI_POWER_CONTROL 0x29 +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_BLOCK_GAP_CONTROL 0x2A + +#define SDHCI_WAKE_UP_CONTROL 0x2B + +#define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_MASK 0xff +#define SDHCI_DIVIDER_MASK_LEN 8 +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_MASK 3 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001 +#define SDHCI_DIVIDERS_MASK \ ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \ (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT)) -#define SDHCI_TIMEOUT_CONTROL 0x2E +#define SDHCI_TIMEOUT_CONTROL 0x2E -#define SDHCI_SOFTWARE_RESET 0x2F -#define SDHCI_RESET_ALL 0x01 -#define SDHCI_RESET_CMD 0x02 -#define SDHCI_RESET_DATA 0x04 - -#define SDHCI_INT_STATUS 0x30 -#define SDHCI_INT_ENABLE 0x34 -#define SDHCI_SIGNAL_ENABLE 0x38 -#define SDHCI_INT_RESPONSE 0x00000001 -#define SDHCI_INT_DATA_END 0x00000002 -#define SDHCI_INT_BLOCK_GAP 0x00000004 -#define SDHCI_INT_DMA_END 0x00000008 -#define SDHCI_INT_SPACE_AVAIL 0x00000010 -#define SDHCI_INT_DATA_AVAIL 0x00000020 -#define SDHCI_INT_CARD_INSERT 0x00000040 -#define SDHCI_INT_CARD_REMOVE 0x00000080 -#define SDHCI_INT_CARD_INT 0x00000100 -#define SDHCI_INT_INT_A 0x00000200 -#define SDHCI_INT_INT_B 0x00000400 -#define SDHCI_INT_INT_C 0x00000800 -#define SDHCI_INT_RETUNE 0x00001000 -#define SDHCI_INT_ERROR 0x00008000 -#define SDHCI_INT_TIMEOUT 0x00010000 -#define SDHCI_INT_CRC 0x00020000 -#define SDHCI_INT_END_BIT 0x00040000 -#define SDHCI_INT_INDEX 0x00080000 -#define SDHCI_INT_DATA_TIMEOUT 0x00100000 -#define SDHCI_INT_DATA_CRC 0x00200000 -#define SDHCI_INT_DATA_END_BIT 0x00400000 -#define SDHCI_INT_BUS_POWER 0x00800000 -#define SDHCI_INT_ACMD12ERR 0x01000000 -#define SDHCI_INT_ADMAERR 0x02000000 -#define SDHCI_INT_TUNEERR 0x04000000 +#define SDHCI_SOFTWARE_RESET 0x2F +#define SDHCI_RESET_ALL 0x01 +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 + +#define SDHCI_INT_STATUS 0x30 +#define SDHCI_INT_ENABLE 0x34 +#define SDHCI_SIGNAL_ENABLE 0x38 +#define SDHCI_INT_RESPONSE 0x00000001 +#define SDHCI_INT_DATA_END 0x00000002 +#define SDHCI_INT_BLOCK_GAP 0x00000004 +#define SDHCI_INT_DMA_END 0x00000008 +#define SDHCI_INT_SPACE_AVAIL 0x00000010 +#define SDHCI_INT_DATA_AVAIL 0x00000020 +#define SDHCI_INT_CARD_INSERT 0x00000040 +#define SDHCI_INT_CARD_REMOVE 0x00000080 +#define SDHCI_INT_CARD_INT 0x00000100 +#define SDHCI_INT_INT_A 0x00000200 +#define SDHCI_INT_INT_B 0x00000400 +#define SDHCI_INT_INT_C 0x00000800 +#define SDHCI_INT_RETUNE 0x00001000 +#define SDHCI_INT_ERROR 0x00008000 +#define SDHCI_INT_TIMEOUT 0x00010000 +#define SDHCI_INT_CRC 0x00020000 +#define SDHCI_INT_END_BIT 0x00040000 +#define SDHCI_INT_INDEX 0x00080000 +#define SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define SDHCI_INT_DATA_CRC 0x00200000 +#define SDHCI_INT_DATA_END_BIT 0x00400000 +#define SDHCI_INT_BUS_POWER 0x00800000 +#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_ADMAERR 0x02000000 +#define SDHCI_INT_TUNEERR 0x04000000 -#define SDHCI_INT_NORMAL_MASK 0x00007FFF -#define SDHCI_INT_ERROR_MASK 0xFFFF8000 +#define SDHCI_INT_NORMAL_MASK 0x00007FFF +#define SDHCI_INT_ERROR_MASK 0xFFFF8000 -#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ +#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) -#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) +#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) -#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ +#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ SDHCI_INT_DATA_END_BIT) -#define SDHCI_ACMD12_ERR 0x3C -#define SDHCI_HOST_CONTROL2 0x3E +#define SDHCI_ACMD12_ERR 0x3C +#define SDHCI_HOST_CONTROL2 0x3E -#define SDHCI_CAPABILITIES 0x40 -#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F -#define SDHCI_TIMEOUT_CLK_SHIFT 0 -#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 -#define SDHCI_CLOCK_BASE_MASK 0x00003F00 -#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 -#define SDHCI_CLOCK_BASE_SHIFT 8 -#define SDHCI_MAX_BLOCK_MASK 0x00030000 -#define SDHCI_MAX_BLOCK_SHIFT 16 -#define SDHCI_CAN_DO_8BITBUS 0x00040000 -#define SDHCI_CAN_DO_ADMA2 0x00080000 -#define SDHCI_CAN_DO_HISPD 0x00200000 -#define SDHCI_CAN_DO_DMA 0x00400000 -#define SDHCI_CAN_DO_SUSPEND 0x00800000 -#define SDHCI_CAN_VDD_330 0x01000000 -#define SDHCI_CAN_VDD_300 0x02000000 -#define SDHCI_CAN_VDD_180 0x04000000 -#define SDHCI_CAN_DO_64BIT 0x10000000 -#define SDHCI_CAN_ASYNC_INTR 0x20000000 - -#define SDHCI_CAPABILITIES2 0x44 -#define SDHCI_CAN_SDR50 0x00000001 -#define SDHCI_CAN_SDR104 0x00000002 -#define SDHCI_CAN_DDR50 0x00000004 -#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 -#define SDHCI_CAN_DRIVE_TYPE_B 0x00000020 -#define SDHCI_CAN_DRIVE_TYPE_C 0x00000040 -#define SDHCI_RETUNE_CNT_MASK 0x00000F00 -#define SDHCI_RETUNE_CNT_SHIFT 8 -#define SDHCI_TUNE_SDR50 0x00002000 -#define SDHCI_RETUNE_MODES_MASK 0x0000C000 -#define SDHCI_RETUNE_MODES_SHIFT 14 -#define SDHCI_CLOCK_MULT_MASK 0x00FF0000 -#define SDHCI_CLOCK_MULT_SHIFT 16 - -#define SDHCI_MAX_CURRENT 0x48 -#define SDHCI_FORCE_AUTO_EVENT 0x50 -#define SDHCI_FORCE_INTR_EVENT 0x52 -#define SDHCI_ADMA_ERR 0x54 -#define SDHCI_ADMA_ADDRESS_LOW 0x58 -#define SDHCI_ADMA_ADDRESS_HI 0x5C -#define SDHCI_PRESET_VALUE 0x60 -#define SDHCI_SHARED_BUS_CTRL 0xE0 - -#define SDHCI_SLOT_INT_STATUS 0xFC - -#define SDHCI_HOST_VERSION 0xFE -#define SDHCI_VENDOR_VER_MASK 0xFF00 -#define SDHCI_VENDOR_VER_SHIFT 8 -#define SDHCI_SPEC_VER_MASK 0x00FF -#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_CAPABILITIES 0x40 +#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F +#define SDHCI_TIMEOUT_CLK_SHIFT 0 +#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 +#define SDHCI_CLOCK_BASE_MASK 0x00003F00 +#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 +#define SDHCI_CLOCK_BASE_SHIFT 8 +#define SDHCI_MAX_BLOCK_MASK 0x00030000 +#define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_8BITBUS 0x00040000 +#define SDHCI_CAN_DO_ADMA2 0x00080000 +#define SDHCI_CAN_DO_HISPD 0x00200000 +#define SDHCI_CAN_DO_DMA 0x00400000 +#define SDHCI_CAN_DO_SUSPEND 0x00800000 +#define SDHCI_CAN_VDD_330 0x01000000 +#define SDHCI_CAN_VDD_300 0x02000000 +#define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_DO_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INTR 0x20000000 + +#define SDHCI_CAPABILITIES2 0x44 +#define SDHCI_CAN_SDR50 0x00000001 +#define SDHCI_CAN_SDR104 0x00000002 +#define SDHCI_CAN_DDR50 0x00000004 +#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 +#define SDHCI_CAN_DRIVE_TYPE_B 0x00000020 +#define SDHCI_CAN_DRIVE_TYPE_C 0x00000040 +#define SDHCI_RETUNE_CNT_MASK 0x00000F00 +#define SDHCI_RETUNE_CNT_SHIFT 8 +#define SDHCI_TUNE_SDR50 0x00002000 +#define SDHCI_RETUNE_MODES_MASK 0x0000C000 +#define SDHCI_RETUNE_MODES_SHIFT 14 +#define SDHCI_CLOCK_MULT_MASK 0x00FF0000 +#define SDHCI_CLOCK_MULT_SHIFT 16 + +#define SDHCI_MAX_CURRENT 0x48 +#define SDHCI_FORCE_AUTO_EVENT 0x50 +#define SDHCI_FORCE_INTR_EVENT 0x52 +#define SDHCI_ADMA_ERR 0x54 +#define SDHCI_ADMA_ADDRESS_LOW 0x58 +#define SDHCI_ADMA_ADDRESS_HI 0x5C +#define SDHCI_PRESET_VALUE 0x60 +#define SDHCI_SHARED_BUS_CTRL 0xE0 + +#define SDHCI_SLOT_INT_STATUS 0xFC + +#define SDHCI_HOST_VERSION 0xFE +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 @@ -310,10 +310,10 @@ struct sdhci_slot { u_char cmd_done; /* CMD command part done flag */ u_char data_done; /* DAT command part done flag */ u_char flags; /* Request execution flags */ -#define CMD_STARTED 1 -#define STOP_STARTED 2 -#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ -#define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ +#define CMD_STARTED 1 +#define STOP_STARTED 2 +#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ +#define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ struct mtx mtx; /* Slot mutex */ }; Modified: head/sys/dev/sdhci/sdhci_fdt.c ============================================================================== --- head/sys/dev/sdhci/sdhci_fdt.c Sat Feb 4 19:16:19 2017 (r313249) +++ head/sys/dev/sdhci/sdhci_fdt.c Sat Feb 4 19:35:38 2017 (r313250) @@ -60,7 +60,7 @@ __FBSDID("$FreeBSD$"); #include "mmcbr_if.h" #include "sdhci_if.h" -#define MAX_SLOTS 6 +#define MAX_SLOTS 6 struct sdhci_fdt_softc { device_t dev; /* Controller device */ @@ -68,7 +68,7 @@ struct sdhci_fdt_softc { u_int caps; /* If we override SDHCI_CAPABILITIES */ uint32_t max_clk; /* Max possible freq */ struct resource *irq_res; /* IRQ resource */ - void *intrhand; /* Interrupt handle */ + void *intrhand; /* Interrupt handle */ int num_slots; /* Number of slots on this controller*/ struct sdhci_slot slots[MAX_SLOTS]; @@ -79,14 +79,16 @@ static uint8_t sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + return (bus_read_1(sc->mem_res[slot->num], off)); } static void sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, - uint8_t val) + uint8_t val) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + bus_write_1(sc->mem_res[slot->num], off, val); } @@ -94,14 +96,16 @@ static uint16_t sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + return (bus_read_2(sc->mem_res[slot->num], off)); } static void sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, - uint16_t val) + uint16_t val) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + bus_write_2(sc->mem_res[slot->num], off, val); } @@ -109,14 +113,16 @@ static uint32_t sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + return (bus_read_4(sc->mem_res[slot->num], off)); } static void sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, - uint32_t val) + uint32_t val) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + bus_write_4(sc->mem_res[slot->num], off, val); } @@ -125,6 +131,7 @@ sdhci_fdt_read_multi_4(device_t dev, str bus_size_t off, uint32_t *data, bus_size_t count) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + bus_read_multi_4(sc->mem_res[slot->num], off, data, count); } @@ -133,6 +140,7 @@ sdhci_fdt_write_multi_4(device_t dev, st bus_size_t off, uint32_t *data, bus_size_t count) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + bus_write_multi_4(sc->mem_res[slot->num], off, data, count); } @@ -142,10 +150,8 @@ sdhci_fdt_intr(void *arg) struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg; int i; - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - sdhci_generic_intr(slot); - } + for (i = 0; i < sc->num_slots; i++) + sdhci_generic_intr(&sc->slots[i]); } static int @@ -187,6 +193,7 @@ static int sdhci_fdt_attach(device_t dev) { struct sdhci_fdt_softc *sc = device_get_softc(dev); + struct sdhci_slot *slot; int err, slots, rid, i; sc->dev = dev; @@ -194,7 +201,7 @@ sdhci_fdt_attach(device_t dev) /* Allocate IRQ. */ rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, - RF_ACTIVE); + RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(dev, "Can't allocate IRQ\n"); return (ENOMEM); @@ -204,15 +211,15 @@ sdhci_fdt_attach(device_t dev) slots = sc->num_slots; /* number of slots determined in probe(). */ sc->num_slots = 0; for (i = 0; i < slots; i++) { - struct sdhci_slot *slot = &sc->slots[sc->num_slots]; + slot = &sc->slots[sc->num_slots]; /* Allocate memory. */ rid = 0; sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res[i] == NULL) { - device_printf(dev, "Can't allocate memory for " - "slot %d\n", i); + device_printf(dev, + "Can't allocate memory for slot %d\n", i); continue; } @@ -236,10 +243,8 @@ sdhci_fdt_attach(device_t dev) } /* Process cards detection. */ - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - sdhci_start_slot(slot); - } + for (i = 0; i < sc->num_slots; i++) + sdhci_start_slot(&sc->slots[i]); *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***