Date: Thu, 3 Dec 2009 04:06:48 +0000 (UTC) From: Marcel Moolenaar <marcel@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/ia64/ia64 machdep.c src/sys/ia64/include bus.h cpufunc.h ia64_cpu.h Message-ID: <200912030406.nB346vFg090306@repoman.freebsd.org>
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marcel 2009-12-03 04:06:48 UTC FreeBSD src repository Modified files: sys/ia64/ia64 machdep.c sys/ia64/include bus.h cpufunc.h ia64_cpu.h Log: SVN rev 200051 on 2009-12-03 04:06:48Z by marcel Make sure bus space accesses use unorder memory loads and stores. Memory accesses are posted in program order by virtue of the uncacheable memory attribute. Since GCC, by default, adds acquire and release semantics to volatile memory loads and stores, we need to use inline assembly to guarantee it. With inline assembly, we don't need volatile pointers anymore. Itanium does not support semaphore instructions to uncacheable memory. Revision Changes Path 1.250 +2 -2 src/sys/ia64/ia64/machdep.c 1.23 +76 -76 src/sys/ia64/include/bus.h 1.24 +2 -2 src/sys/ia64/include/cpufunc.h 1.25 +68 -0 src/sys/ia64/include/ia64_cpu.h
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