From owner-svn-src-stable-11@freebsd.org Fri Apr 14 14:48:57 2017 Return-Path: Delivered-To: svn-src-stable-11@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3138AD3D631; Fri, 14 Apr 2017 14:48:57 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id DD423325; Fri, 14 Apr 2017 14:48:56 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v3EEmuUa075060; Fri, 14 Apr 2017 14:48:56 GMT (envelope-from avg@FreeBSD.org) Received: (from avg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v3EEmuhk075059; Fri, 14 Apr 2017 14:48:56 GMT (envelope-from avg@FreeBSD.org) Message-Id: <201704141448.v3EEmuhk075059@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: avg set sender to avg@FreeBSD.org using -f From: Andriy Gapon Date: Fri, 14 Apr 2017 14:48:56 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r316844 - stable/11/sys/x86/x86 X-SVN-Group: stable-11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-11@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for only the 11-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Apr 2017 14:48:57 -0000 Author: avg Date: Fri Apr 14 14:48:55 2017 New Revision: 316844 URL: https://svnweb.freebsd.org/changeset/base/316844 Log: MFC r316017,r316020: add SMT detection for newer AMD processors Modified: stable/11/sys/x86/x86/mp_x86.c Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/x86/x86/mp_x86.c ============================================================================== --- stable/11/sys/x86/x86/mp_x86.c Fri Apr 14 14:45:44 2017 (r316843) +++ stable/11/sys/x86/x86/mp_x86.c Fri Apr 14 14:48:55 2017 (r316844) @@ -226,11 +226,10 @@ add_deterministic_cache(int type, int le * Determine topology of processing units and caches for AMD CPUs. * See: * - AMD CPUID Specification (Publication # 25481) - * - BKDG For AMD Family 10h Processors (Publication # 31116), section 2.15 * - BKDG for AMD NPT Family 0Fh Processors (Publication # 32559) - * XXX At the moment the code does not recognize grouping of AMD CMT threads, - * if supported, into cores, so each thread is treated as being in its own - * core. In other words, each logical CPU is considered to be a core. + * - BKDG For AMD Family 10h Processors (Publication # 31116) + * - BKDG For AMD Family 15h Models 00h-0Fh Processors (Publication # 42301) + * - BKDG For AMD Family 16h Models 00h-0Fh Processors (Publication # 48751) */ static void topo_probe_amd(void) @@ -254,6 +253,22 @@ topo_probe_amd(void) pkg_id_shift = mask_width((cpu_procinfo2 & AMDID_CMP_CORES) + 1); + /* + * Families prior to 16h define the following value as + * cores per compute unit and we don't really care about the AMD + * compute units at the moment. Perhaps we should treat them as + * cores and cores within the compute units as hardware threads, + * but that's up for debate. + * Later families define the value as threads per compute unit, + * so we are following AMD's nomenclature here. + */ + if ((amd_feature2 & AMDID2_TOPOLOGY) != 0 && + CPUID_TO_FAMILY(cpu_id) >= 0x16) { + cpuid_count(0x8000001e, 0, p); + share_count = ((p[1] >> 8) & 0xff) + 1; + core_id_shift = mask_width(share_count); + } + if ((amd_feature2 & AMDID2_TOPOLOGY) != 0) { for (i = 0; ; i++) { cpuid_count(0x8000001d, i, p);