Date: Sun, 22 Jan 95 22:24 CST From: steve@simon.chi.il.us (Steven E. Piette) To: hackers@FreeBSD.org Cc: davidg@Root.COM, jgreco@ns.sol.net, phk@ref.tfs.com Subject: Re: SMC EtherEZ PnP Message-ID: <m0rWGKV-000NAvC@simon.chi.il.us>
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> To: steve@simon.chi.il.us (Steven E. Piette)
> cc: jgreco@ns.sol.net, phk@ref.tfs.com
> Subject: Re: SMC EtherEZ PnP
> From: David Greenman <davidg@Root.COM>
>
> >Back in October, there was some interest in the details of this new SMC
> >adaptor. For $49 even if I couldn't use it with FreeBSD right off, it was
> >a bargin. It could always replace the old 3C501 in the DOS machine :-)
> >So, I got one.
> >
> >Here's the spec sheet that comes with:
> >
> >They also claim that "The EtherEZ adaptor, when in its optional Memory
> >Mapped Adressing Mode, is compatable with SMC drivers developed for the
> >EtherCard Elite16 Ultra adaptor, and drivers created by other developers."
> >
> >We'll see .....
>
> It needs a patch to the driver before it will work. You might be able to
> get it to work by setting 'iosiz 8192' in the kernel config file.
> Unfortunately, 'iosiz' isn't settable in userconfig (-c on startup). That
> needs to be fixed...
>
> -DG
>
I've received the SMC 83C795 Tech spec and done a quick hack which seems to
work with both the SMC Ultra Elite (8216C) and the SMC EtherEZ (8316C) cards.
The patch just reads the apparent size of buffer window from the asic and sets
memsize to reflect that.
I've tested with both here, so here's the diffs so others can try it out.
*** if_ed.c.orig Thu Nov 17 08:42:27 1994
--- if_ed.c Sat Jan 21 13:19:21 1995
***************
*** 408,413 ****
--- 408,437 ----
isa16bit = 0;
memsize = 8192;
}
+
+
+ if (sc->is790) {
+ outb(sc->asic_addr + ED_WD790_HWR,
+ inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
+
+ switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
+ case ED_WD790_RAR_SZ64:
+ memsize = 65536;
+ break;
+ case ED_WD790_RAR_SZ32:
+ memsize = 32768;
+ break;
+ case ED_WD790_RAR_SZ16:
+ memsize = 16384;
+ break;
+ case ED_WD790_RAR_SZ8:
+ memsize = 8192;
+ break;
+ }
+ outb(sc->asic_addr + ED_WD790_HWR,
+ inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
+ }
+
#if ED_DEBUG
printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
***************
*** 546,556 ****
sc->cr_proto = ED_CR_RD2;
} else {
outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
! outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
! outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
((kvtop(sc->mem_start) >> 11) & 0x40) |
! (inb(sc->asic_addr + 0x0b) & 0xb0));
! outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
sc->cr_proto = 0;
}
--- 570,580 ----
sc->cr_proto = ED_CR_RD2;
} else {
outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
! outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
! outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
((kvtop(sc->mem_start) >> 11) & 0x40) |
! (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
! outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
sc->cr_proto = 0;
}
*** if_edreg.h.orig Thu Aug 4 12:42:35 1994
--- if_edreg.h Sat Jan 21 13:23:31 1995
***************
*** 705,710 ****
--- 705,729 ----
#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
/*
+ * REV/IOPA Revision / I/O Pipe register for the 83C79X
+ */
+ #define ED_WD790_REV 7
+
+ #define ED_WD790 0x20
+ #define ED_WD795 0x40
+
+ /*
+ * 79X RAM Address Register (RAR)
+ * Enabled with SWH bit=1 in HWR register
+ */
+ #define ED_WD790_RAR 0x0b
+
+ #define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
+ #define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
+ #define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
+ #define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
+
+ /*
* General Control Register (GCR)
* Enabled with SWH bit=1 in HWR register
*/
***************
*** 714,719 ****
--- 733,739 ----
#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
+ #define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */
/*
* The three bits of the encoded IRQ are decoded as follows:
*
Steve Piette Applied Computer Technology
steve@simon.chi.il.US. 7N852 Phar Lap Drive
(708) 513-6920 St. Charles, IL 60175-6868
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