From owner-svn-soc-all@FreeBSD.ORG Sat Aug 11 16:18:15 2012 Return-Path: Delivered-To: svn-soc-all@FreeBSD.org Received: from socsvn.FreeBSD.org (unknown [IPv6:2001:4f8:fff6::2f]) by hub.freebsd.org (Postfix) with SMTP id 7DA471065672 for ; Sat, 11 Aug 2012 16:18:13 +0000 (UTC) (envelope-from aleek@FreeBSD.org) Received: by socsvn.FreeBSD.org (sSMTP sendmail emulation); Sat, 11 Aug 2012 16:18:13 +0000 Date: Sat, 11 Aug 2012 16:18:13 +0000 From: aleek@FreeBSD.org To: svn-soc-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-Id: <20120811161813.7DA471065672@hub.freebsd.org> Cc: Subject: socsvn commit: r240274 - in soc2012/aleek/beaglexm-armv6/sys/arm: conf ti/twl ti/usb X-BeenThere: svn-soc-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the entire Summer of Code repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Aug 2012 16:18:15 -0000 Author: aleek Date: Sat Aug 11 16:18:11 2012 New Revision: 240274 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=240274 Log: USB EHCI OMAP testing. Ive found some issues about phy resetting, but the patches dont work Modified: soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl.c soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c Modified: soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM Sat Aug 11 15:47:22 2012 (r240273) +++ soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM Sat Aug 11 16:18:11 2012 (r240274) @@ -82,7 +82,7 @@ device mmcsd # mmc/sd flash cards # Boot device is 2nd slice on MMC/SD card -options ROOTDEVNAME=\"msdosfs:mmcsd0s3\" +options ROOTDEVNAME=\"msdosfs:mmcsd0s2\" # Console and misc Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl.c ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl.c Sat Aug 11 15:47:22 2012 (r240273) +++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl.c Sat Aug 11 16:18:11 2012 (r240274) @@ -419,7 +419,6 @@ return (ENOMEM); /* FIXME: should be in DTS file */ - device_printf( dev, "habababa\n" ); if ((sc->sc_vreg = device_add_child(dev, "twl_vreg", -1)) == NULL) device_printf(dev, "could not allocate twl_vreg instance\n"); if ((sc->sc_clks = device_add_child(dev, "twl_clks", -1)) == NULL) Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c ============================================================================== --- soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c Sat Aug 11 15:47:22 2012 (r240273) +++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/usb/omap_ehci.c Sat Aug 11 16:18:11 2012 (r240274) @@ -350,35 +350,53 @@ uint32_t reg = 0; int reset_performed = 0; int i; +// int gpio_val; device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n"); /* Enable Clocks for high speed USBHOST */ - ti_prcm_clk_enable(USBHSHOST_CLK); + if( ti_prcm_clk_enable(USBHSHOST_CLK) != 0 ) + { + device_printf( isc->sc_dev, "KURWAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA" ); + } /* enabling TWL4030/TPS95950 voltage regulator */ - twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb1v5", 1800); - twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb1v8", 1800); - twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb3v1", 1800); + //twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb1v5", 1500); + //twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb1v8", 1800); + //twl_vreg_set_voltage(isc->sc_vreg_dev, "vusb3v1", 3100); /* Hold the PHY in reset while configuring */ + /* for (int i = 0; i < 3; i++) { if (isc->phy_reset[i]) { - /* Configure the GPIO to drive low (hold in reset) */ + // Configure the GPIO to drive low (hold in reset) if ((isc->reset_gpio_pin[i] != -1) && (isc->sc_gpio_dev != NULL)) { GPIO_PIN_SETFLAGS(isc->sc_gpio_dev, isc->reset_gpio_pin[i], GPIO_PIN_OUTPUT); - GPIO_PIN_SET(isc->sc_gpio_dev, isc->reset_gpio_pin[i], - GPIO_PIN_LOW); + if( GPIO_PIN_SET(isc->sc_gpio_dev, isc->reset_gpio_pin[i], + GPIO_PIN_LOW) != 0 ) + { + return ENXIO; + } + if( GPIO_PIN_SET(isc->sc_gpio_dev, 56, + GPIO_PIN_LOW) != 0 ) + { + return ENXIO; + } + GPIO_PIN_GET( isc->sc_gpio_dev, isc->reset_gpio_pin[i], &gpio_val ); + if( gpio_val != GPIO_PIN_LOW ) + { + return ENXIO; + } reset_performed = 1; } } } - +*/ /* Hold the PHY in RESET for enough time till DIR is high */ - if (reset_performed) - DELAY(10); + //if (reset_performed) + DELAY(100); /* Read the UHH revision */ isc->ehci_rev = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_REVISION); @@ -388,7 +406,10 @@ if (isc->ehci_rev == OMAP_EHCI_REV1) { /* Enable the USB TLL */ - ti_prcm_clk_enable(USBTLL_CLK); + if( ti_prcm_clk_enable(USBTLL_CLK) != 0 ) + { + device_printf( isc->sc_dev, "AKURWAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA" ); + } //omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG04, OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND); @@ -524,10 +545,8 @@ * the root-hub is allowed to suspend. Writing 1 to this undocumented * register bit disables this feature and restores normal behavior." */ -#if 0 omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG04, OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND); -#endif /* If any of the ports are configured in TLL mode, enable them */ if ((isc->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) || @@ -545,14 +564,6 @@ omap_ehci_utmi_init(isc, tll_ch_mask); } - /* Soft reset the PHY using PHY reset command over ULPI */ - if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) - omap_ehci_soft_phy_reset(isc, 0); - if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) - omap_ehci_soft_phy_reset(isc, 1); - - //ehci_reset( isc->base ); - /* Release the PHY reset signal now we have configured everything */ if (reset_performed) { @@ -566,10 +577,17 @@ && (isc->sc_gpio_dev != NULL)) { GPIO_PIN_SET(isc->sc_gpio_dev, isc->reset_gpio_pin[i], GPIO_PIN_HIGH); + GPIO_PIN_SET(isc->sc_gpio_dev, + 56, GPIO_PIN_HIGH); } } } + /* Soft reset the PHY using PHY reset command over ULPI */ + if (isc->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) + omap_ehci_soft_phy_reset(isc, 0); + if (isc->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) + omap_ehci_soft_phy_reset(isc, 1); /* Set the interrupt threshold control, it controls the maximum rate at * which the host controller issues interrupts. We set it to 1 microframe * at startup - the default is 8 mircoframes (equates to 1ms).