From owner-svn-src-head@freebsd.org Sat Mar 4 21:47:45 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 28538CF5E52; Sat, 4 Mar 2017 21:47:45 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D14CA11DA; Sat, 4 Mar 2017 21:47:44 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v24LlhW0088031; Sat, 4 Mar 2017 21:47:43 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v24Llh2k088030; Sat, 4 Mar 2017 21:47:43 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201703042147.v24Llh2k088030@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sat, 4 Mar 2017 21:47:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r314681 - head/sys/dev/uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 Mar 2017 21:47:45 -0000 Author: ian Date: Sat Mar 4 21:47:43 2017 New Revision: 314681 URL: https://svnweb.freebsd.org/changeset/base/314681 Log: Fix bugs exposed by the recent enabling of FIFOs in the pl011 uart. These have been in the code all along, but were masked by having a fifo depth of one byte at the hardware level, so everything kinda worked by accident. The hardware interrupts when the TX fifo is half empty, so set sc->sc_txfifosz to 8 bytes (half the hardware fifo size) to match. This eliminates dropped characters on output. Restructure the read loop to consume all the bytes in the fifo by using the "rx fifo empty" bit of the flags register rather than the "rx ready" bit of the interrupt status register. The rx-ready interrupt is cleared when the number of bytes in the fifo fall below the interrupt trigger level, leaving the fifo half full every time receive routine was called. Now it loops until the fifo is completely empty every time (including when the function is called due to a receive timeout as well as for fifo-full). Modified: head/sys/dev/uart/uart_dev_pl011.c Modified: head/sys/dev/uart/uart_dev_pl011.c ============================================================================== --- head/sys/dev/uart/uart_dev_pl011.c Sat Mar 4 21:32:23 2017 (r314680) +++ head/sys/dev/uart/uart_dev_pl011.c Sat Mar 4 21:47:43 2017 (r314681) @@ -419,7 +419,7 @@ uart_pl011_bus_probe(struct uart_softc * device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); sc->sc_rxfifosz = 16; - sc->sc_txfifosz = 16; + sc->sc_txfifosz = 8; return (0); } @@ -434,8 +434,10 @@ uart_pl011_bus_receive(struct uart_softc bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - ints = __uart_getreg(bas, UART_MIS); - while (ints & (UART_RXREADY | RIS_RTIM)) { + for (;;) { + ints = __uart_getreg(bas, UART_FR); + if (ints & FR_RXFE) + break; if (uart_rx_full(sc)) { sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; @@ -450,7 +452,6 @@ uart_pl011_bus_receive(struct uart_softc rx |= UART_STAT_PARERR; uart_rx_put(sc, rx); - ints = __uart_getreg(bas, UART_MIS); } uart_unlock(sc->sc_hwmtx);