From owner-svn-src-head@FreeBSD.ORG Mon Nov 19 23:04:23 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 6D72FB78; Mon, 19 Nov 2012 23:04:23 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 380768FC0C; Mon, 19 Nov 2012 23:04:23 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qAJN4Nmp059233; Mon, 19 Nov 2012 23:04:23 GMT (envelope-from jkim@svn.freebsd.org) Received: (from jkim@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qAJN4Nx9059232; Mon, 19 Nov 2012 23:04:23 GMT (envelope-from jkim@svn.freebsd.org) Message-Id: <201211192304.qAJN4Nx9059232@svn.freebsd.org> From: Jung-uk Kim Date: Mon, 19 Nov 2012 23:04:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r243315 - head/share/examples/etc X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 23:04:23 -0000 Author: jkim Date: Mon Nov 19 23:04:22 2012 New Revision: 243315 URL: http://svnweb.freebsd.org/changeset/base/243315 Log: Clean up and update comments for CPUTYPE. Requested by: rdivacky Modified: head/share/examples/etc/make.conf Modified: head/share/examples/etc/make.conf ============================================================================== --- head/share/examples/etc/make.conf Mon Nov 19 22:56:51 2012 (r243314) +++ head/share/examples/etc/make.conf Mon Nov 19 23:04:22 2012 (r243315) @@ -25,22 +25,27 @@ # The CPUTYPE variable controls which processor should be targeted for # generated code. This controls processor-specific optimizations in # certain code (currently only OpenSSL) as well as modifying the value -# of CFLAGS to contain the appropriate optimization directive to gcc. +# of CFLAGS to contain the appropriate optimization directive to cc. # The automatic setting of CFLAGS may be overridden using the # NO_CPU_CFLAGS variable below. -# Currently the following CPU types are recognized: +# Currently the following CPU types are recognized by gcc: # Intel x86 architecture: -# (AMD CPUs) opteron-sse3 opteron athlon64-sse3 athlon64 athlon-mp -# athlon-xp athlon-4 athlon-tbird athlon k8-sse3 k8 -# geode k6-3 k6-2 k6 k5 -# (Intel CPUs) core2 core nocona pentium4m pentium4 prescott -# pentium3m pentium3 pentium-m pentium2 -# pentiumpro pentium-mmx pentium i486 i386 -# (Via CPUs) c3 c3-2 -# AMD64 architecture: opteron, athlon64, nocona, prescott, core2 -# Intel ia64 architecture: itanium2, itanium +# (AMD CPUs) opteron-sse3, athlon64-sse3, k8-sse3, opteron, +# athlon64, k8, athlon-mp, athlon-xp, athlon-4, +# athlon-tbird, athlon, k7, geode, k6-3, k6-2, k6, k5 +# (Intel CPUs) core2, core, nocona, pentium4m, pentium4, prescott, +# pentium3m, pentium3, pentium-m, pentium2, +# pentiumpro, pentium-mmx, pentium, i486, i386 +# (VIA CPUs) c7, c3-2, c3 +# AMD64 architecture: opteron-sse3, athlon64-sse3, k8-sse3, opteron, +# athlon64, k8, core2, nocona, prescott +# Intel ia64 architecture: itanium2, itanium # SPARC-V9 architecture: v9 (generic 64-bit V9), ultrasparc (default # if omitted), ultrasparc3 +# Additionally the following CPU types are recognized by clang: +# Intel x86 architecture (for both amd64 and i386): +# (AMD CPUs) bdver2, bdver1, btver1, amdfam10 +# (Intel CPUs) core-avx-i, corei7-avx, corei7 # # (?= allows to buildworld for a different CPUTYPE.) #