From owner-svn-src-head@freebsd.org Mon Mar 25 18:02:05 2019 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 905F81548018; Mon, 25 Mar 2019 18:02:05 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 33008805A5; Mon, 25 Mar 2019 18:02:05 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 289B0B6ED; Mon, 25 Mar 2019 18:02:05 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x2PI25lu097025; Mon, 25 Mar 2019 18:02:05 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x2PI25UO097024; Mon, 25 Mar 2019 18:02:05 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201903251802.x2PI25UO097024@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Mon, 25 Mar 2019 18:02:05 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r345510 - head/sys/arm64/arm64 X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: head/sys/arm64/arm64 X-SVN-Commit-Revision: 345510 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 33008805A5 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.97 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_SHORT(-0.97)[-0.972,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0] X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Mar 2019 18:02:05 -0000 Author: andrew Date: Mon Mar 25 18:02:04 2019 New Revision: 345510 URL: https://svnweb.freebsd.org/changeset/base/345510 Log: Sort printing of the ID registers on arm64 to be identical to the documentation. This will simplify checking new fields when they are added. MFC after: 2 weeks Sponsored by: DARPA, AFRL Modified: head/sys/arm64/arm64/identcpu.c Modified: head/sys/arm64/arm64/identcpu.c ============================================================================== --- head/sys/arm64/arm64/identcpu.c Mon Mar 25 17:45:47 2019 (r345509) +++ head/sys/arm64/arm64/identcpu.c Mon Mar 25 18:02:04 2019 (r345510) @@ -494,63 +494,68 @@ print_cpu_features(u_int cpu) printed = 0; sbuf_printf(sb, " Instruction Set Attributes 0 = <"); - switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_RDM_NONE: + switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_DP_NONE: break; - case ID_AA64ISAR0_RDM_IMPL: - sbuf_printf(sb, "%sRDM", SEP_STR); + case ID_AA64ISAR0_DP_IMPL: + sbuf_printf(sb, "%sDotProd", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown RDM", SEP_STR); + sbuf_printf(sb, "%sUnknown DP", SEP_STR); + break; } - switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_ATOMIC_NONE: + switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SM4_NONE: break; - case ID_AA64ISAR0_ATOMIC_IMPL: - sbuf_printf(sb, "%sAtomic", SEP_STR); + case ID_AA64ISAR0_SM4_IMPL: + sbuf_printf(sb, "%sSM4", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown Atomic", SEP_STR); + sbuf_printf(sb, "%sUnknown SM4", SEP_STR); + break; } - switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_AES_NONE: + switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SM3_NONE: break; - case ID_AA64ISAR0_AES_BASE: - sbuf_printf(sb, "%sAES", SEP_STR); + case ID_AA64ISAR0_SM3_IMPL: + sbuf_printf(sb, "%sSM3", SEP_STR); break; - case ID_AA64ISAR0_AES_PMULL: - sbuf_printf(sb, "%sAES+PMULL", SEP_STR); - break; default: - sbuf_printf(sb, "%sUnknown AES", SEP_STR); + sbuf_printf(sb, "%sUnknown SM3", SEP_STR); break; } - switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SHA1_NONE: + switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SHA3_NONE: break; - case ID_AA64ISAR0_SHA1_BASE: - sbuf_printf(sb, "%sSHA1", SEP_STR); + case ID_AA64ISAR0_SHA3_IMPL: + sbuf_printf(sb, "%sSHA3", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown SHA1", SEP_STR); + sbuf_printf(sb, "%sUnknown SHA3", SEP_STR); break; } - switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SHA2_NONE: + switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_RDM_NONE: break; - case ID_AA64ISAR0_SHA2_BASE: - sbuf_printf(sb, "%sSHA2", SEP_STR); + case ID_AA64ISAR0_RDM_IMPL: + sbuf_printf(sb, "%sRDM", SEP_STR); break; - case ID_AA64ISAR0_SHA2_512: - sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR); - break; default: - sbuf_printf(sb, "%sUnknown SHA2", SEP_STR); + sbuf_printf(sb, "%sUnknown RDM", SEP_STR); + } + + switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_ATOMIC_NONE: break; + case ID_AA64ISAR0_ATOMIC_IMPL: + sbuf_printf(sb, "%sAtomic", SEP_STR); + break; + default: + sbuf_printf(sb, "%sUnknown Atomic", SEP_STR); } switch (ID_AA64ISAR0_CRC32(cpu_desc[cpu].id_aa64isar0)) { @@ -564,47 +569,42 @@ print_cpu_features(u_int cpu) break; } - switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SHA3_NONE: + switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SHA2_NONE: break; - case ID_AA64ISAR0_SHA3_IMPL: - sbuf_printf(sb, "%sSHA3", SEP_STR); + case ID_AA64ISAR0_SHA2_BASE: + sbuf_printf(sb, "%sSHA2", SEP_STR); break; - default: - sbuf_printf(sb, "%sUnknown SHA3", SEP_STR); + case ID_AA64ISAR0_SHA2_512: + sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR); break; - } - - switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SM3_NONE: - break; - case ID_AA64ISAR0_SM3_IMPL: - sbuf_printf(sb, "%sSM3", SEP_STR); - break; default: - sbuf_printf(sb, "%sUnknown SM3", SEP_STR); + sbuf_printf(sb, "%sUnknown SHA2", SEP_STR); break; } - switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_SM4_NONE: + switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_SHA1_NONE: break; - case ID_AA64ISAR0_SM4_IMPL: - sbuf_printf(sb, "%sSM4", SEP_STR); + case ID_AA64ISAR0_SHA1_BASE: + sbuf_printf(sb, "%sSHA1", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown SM4", SEP_STR); + sbuf_printf(sb, "%sUnknown SHA1", SEP_STR); break; } - switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) { - case ID_AA64ISAR0_DP_NONE: + switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) { + case ID_AA64ISAR0_AES_NONE: break; - case ID_AA64ISAR0_DP_IMPL: - sbuf_printf(sb, "%sDotProd", SEP_STR); + case ID_AA64ISAR0_AES_BASE: + sbuf_printf(sb, "%sAES", SEP_STR); break; + case ID_AA64ISAR0_AES_PMULL: + sbuf_printf(sb, "%sAES+PMULL", SEP_STR); + break; default: - sbuf_printf(sb, "%sUnknown DP", SEP_STR); + sbuf_printf(sb, "%sUnknown AES", SEP_STR); break; } @@ -868,17 +868,6 @@ print_cpu_features(u_int cpu) break; } - switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) { - case ID_AA64MMFR0_TGRAN16_NONE: - break; - case ID_AA64MMFR0_TGRAN16_IMPL: - sbuf_printf(sb, "%s16k Granule", SEP_STR); - break; - default: - sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR); - break; - } - switch (ID_AA64MMFR0_TGRAN64(cpu_desc[cpu].id_aa64mmfr0)) { case ID_AA64MMFR0_TGRAN64_NONE: break; @@ -890,14 +879,14 @@ print_cpu_features(u_int cpu) break; } - switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) { - case ID_AA64MMFR0_BIGEND_FIXED: + switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) { + case ID_AA64MMFR0_TGRAN16_NONE: break; - case ID_AA64MMFR0_BIGEND_MIXED: - sbuf_printf(sb, "%sMixedEndian", SEP_STR); + case ID_AA64MMFR0_TGRAN16_IMPL: + sbuf_printf(sb, "%s16k Granule", SEP_STR); break; default: - sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR); + sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR); break; } @@ -920,6 +909,17 @@ print_cpu_features(u_int cpu) break; default: sbuf_printf(sb, "%sUnknown S/NS Mem", SEP_STR); + break; + } + + switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) { + case ID_AA64MMFR0_BIGEND_FIXED: + break; + case ID_AA64MMFR0_BIGEND_MIXED: + sbuf_printf(sb, "%sMixedEndian", SEP_STR); + break; + default: + sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR); break; }