From owner-svn-src-projects@FreeBSD.ORG Thu Dec 5 05:58:18 2013 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 8B26BD06; Thu, 5 Dec 2013 05:58:18 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 46A961F4D; Thu, 5 Dec 2013 05:58:18 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rB55wHtY074194; Thu, 5 Dec 2013 05:58:17 GMT (envelope-from jhibbits@svn.freebsd.org) Received: (from jhibbits@localhost) by svn.freebsd.org (8.14.7/8.14.7/Submit) id rB55wHD3074193; Thu, 5 Dec 2013 05:58:17 GMT (envelope-from jhibbits@svn.freebsd.org) Message-Id: <201312050558.rB55wHD3074193@svn.freebsd.org> From: Justin Hibbits Date: Thu, 5 Dec 2013 05:58:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r258957 - projects/pmac_pmu/sys/powerpc/powermac X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2013 05:58:18 -0000 Author: jhibbits Date: Thu Dec 5 05:58:17 2013 New Revision: 258957 URL: http://svnweb.freebsd.org/changeset/base/258957 Log: Fix the cache flushing code, by flushing the L1 twice. Linux and OS X do this very thing, possibly to work around bugs in the silicon. Without this it doesn't flush completely, and results in memory corruption down the road. Modified: projects/pmac_pmu/sys/powerpc/powermac/platform_powermac.c Modified: projects/pmac_pmu/sys/powerpc/powermac/platform_powermac.c ============================================================================== --- projects/pmac_pmu/sys/powerpc/powermac/platform_powermac.c Thu Dec 5 03:01:41 2013 (r258956) +++ projects/pmac_pmu/sys/powerpc/powermac/platform_powermac.c Thu Dec 5 05:58:17 2013 (r258957) @@ -332,7 +332,7 @@ flush_disable_caches(void) register_t msr; register_t msscr0; register_t cache_reg; - volatile uint32_t *romp; + volatile uint32_t *memp; uint32_t temp; int i; int x; @@ -359,17 +359,30 @@ flush_disable_caches(void) mtspr(SPR_LDSTCR, 0); - romp = (uint32_t *)0xfff00000; + /* + * Perform this in two stages: Flush the cache starting in RAM, then do it + * from ROM. + */ + memp = (volatile uint32_t *)0x00000000; + for (i = 0; i < 128 * 1024; i++) { + temp = *memp; + __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); + memp += 32/sizeof(*memp); + } + + memp = (volatile uint32_t *)0xfff00000; x = 0xfe; for (; x != 0xff;) { mtspr(SPR_LDSTCR, x); for (i = 0; i < 128; i++) { - temp = *romp; - romp += 32/sizeof(*romp); + temp = *memp; + __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); + memp += 32/sizeof(*memp); } x = ((x << 1) | 1) & 0xff; } + mtspr(SPR_LDSTCR, 0); cache_reg = mfspr(SPR_L2CR); if (cache_reg & L2CR_L2E) {