From owner-freebsd-mips@FreeBSD.ORG Thu Jul 2 03:49:01 2009 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E9C5D106566C for ; Thu, 2 Jul 2009 03:49:01 +0000 (UTC) (envelope-from neelnatu@yahoo.com) Received: from web34403.mail.mud.yahoo.com (web34403.mail.mud.yahoo.com [66.163.178.152]) by mx1.freebsd.org (Postfix) with SMTP id B401C8FC17 for ; Thu, 2 Jul 2009 03:49:01 +0000 (UTC) (envelope-from neelnatu@yahoo.com) Received: (qmail 50632 invoked by uid 60001); 2 Jul 2009 03:49:01 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yahoo.com; s=s1024; t=1246506541; bh=0Op1feFGq0uzLeC3Vn5kI+2D9PFfW9nzA/Bml3VQ8Es=; h=Message-ID:X-YMail-OSG:Received:X-Mailer:Date:From:Subject:To:Cc:MIME-Version:Content-Type; b=HRUurr76ZN1edrOew90F/eTb/FLzdXQ4sQ2khmxKcM3Y5ET3omlq0CDCIRs2NtEJA4j/NC1ny4hc5NFT6qfsfEb/2Qx+cgNpBabRwH9sczt7VL98ausnrtG390J9EO/yczTCVgFfj9481ArlsrfKAvpqmrL2whmzdzGXw3lTlNc= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Message-ID:X-YMail-OSG:Received:X-Mailer:Date:From:Subject:To:Cc:MIME-Version:Content-Type; b=6Aiw/AiztiIjWDkt2bReUKmsPRrkAk7mP5r/jRO0ina+LXD9Ll6NpT4dEo9BG6v0khYygf2M6Uh6m+veXVxu3D+4SzNKUOqrNzfVZzyMBrBzFcpz6e8ttEvNBOxTg4rYk+rFCCWtr45lIn7rVUQeRMSpO+WN2WOb/w+HPiE/2o4=; Message-ID: <122643.47019.qm@web34403.mail.mud.yahoo.com> X-YMail-OSG: hdkwIFsVM1nX4hR7XF5XbYWWhp.SDwSunA6a74Mt.gmY75ACIVyqg06EPm6QtuaAF.nq_jtruu4YIzrVfGSHXxzkwn65J5R_c4TANsHqWnNnDS3HO41W2AisEam4aeG6YwN6MZekrCor_sUxzWcQ.lJQ1wCjSvcrD5Jzwgs2MgtNTYVr2g.eIGi_7Nu.FCu0nXESvxKHPyHi5zto3YdJ6QCjkF6Gkg44e_G.fk3EVGxkcjlic.pSiwwdrxLdbS2qeGAQmT1RqfUzXx14DshNMYJg__jTB9XZom1BCGcyVQizFtcOu6Gk0eln5zKijnXHz_oCsGPHJP4XmDQ8FdYKY2LPcw-- Received: from [198.95.226.228] by web34403.mail.mud.yahoo.com via HTTP; Wed, 01 Jul 2009 20:49:01 PDT X-Mailer: YahooMailClassic/5.4.17 YahooMailWebService/0.7.289.15 Date: Wed, 1 Jul 2009 20:49:01 -0700 (PDT) From: Neelkanth Natu To: "M. Warner Losh" MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: freebsd-mips@freebsd.org Subject: Re: Machine Check exception during bootup X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Jul 2009 03:49:02 -0000 Hi Warner, Here is the unified diff: ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c ==== @@ -91,6 +91,7 @@ ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); ASSYM(SIGFPE, SIGFPE); ASSYM(PGSHIFT, PGSHIFT); +ASSYM(PAGE_SHIFT, PAGE_SHIFT); ASSYM(NBPG, NBPG); ASSYM(SEGSHIFT, SEGSHIFT); ASSYM(NPTEPG, NPTEPG); ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== @@ -81,14 +81,12 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 -#define PAGE_SHIFT 34 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 -#define PAGE_SHIFT 2 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -232,22 +230,30 @@ mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address _MFC0 t0, COP_0_TLB_HI # Save the PID - _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 + li v0, MIPS_KSEG0_START # invalid address + addu v0, t3 /* * Align the starting value (t1) and the upper bound (a0). */ 1: mtc0 t1, COP_0_TLB_INDEX # Set the index register. ITLBNOPFIX - _MTC0 t0, COP_0_TLB_HI # Restore the PID + _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid addu t1, t1, 1 # Increment index. - addu t0, t0, 8 * 1024 + addu v0, v0, 8 * 1024 MIPS_CPU_NOP_DELAY tlbwi # Write the TLB entry. MIPS_CPU_NOP_DELAY @@ -289,12 +295,12 @@ tlbp # Probe for the entry. MIPS_CPU_NOP_DELAY mfc0 v0, COP_0_TLB_INDEX # See what we got - li t1, MIPS_KSEG0_START + 0x0fff0000 + li t1, MIPS_KSEG0_START bltz v0, 1f # index < 0 => !found nop # Load invalid entry, each TLB entry should have it's own bogus # address calculated by following expression: - # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; # One bogus value for every TLB entry might cause MCHECK exception sll v0, PAGE_SHIFT + 1 addu t1, v0 @@ -473,7 +479,17 @@ _MFC0 t4, COP_0_TLB_HI # Get current PID move t2, a0 mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 + li v0, MIPS_KSEG0_START # invalid address + addu v0, t3 + mfc0 t3, COP_0_TLB_PG_MASK # save current pgMask # do {} while (t1 < t2) ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/swtch.S#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/swtch.S ==== @@ -81,14 +81,12 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 -#define PAGE_SHIFT 34 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 -#define PAGE_SHIFT 2 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -361,7 +359,7 @@ nop pgm: bltz s0, entry0set - li t1, MIPS_KSEG0_START + 0x0fff0000 # invalidate tlb entry + li t1, MIPS_KSEG0_START # invalidate tlb entry sll s0, PAGE_SHIFT + 1 addu t1, s0 mtc0 t1, COP_0_TLB_HI --- On Wed, 7/1/09, M. Warner Losh wrote: > From: M. Warner Losh > Subject: Re: Machine Check exception during bootup > To: neelnatu@yahoo.com > Cc: freebsd-mips@freebsd.org > Date: Wednesday, July 1, 2009, 8:39 PM > In message: <646809.32414.qm@web34401.mail.mud.yahoo.com> > Neelkanth Natu > > writes: > : > : Hi Warner, > : > : Thanks for reviewing the diff. > : > : I have made the changes you suggested in the review. The > new diffs are > : at the end of this email. > : > : - No need to have redefine PAGE_SIZE in tlb.S. I am now > generating > : this macro via genassym.c > : > : - Remove the offset 0x0fff0000 used when invalidating tlb > entries. I have > : tested this on MALTA as well as SWARM > and it seems to work fine. > > Yes. You fixed the real bug, I think, when you moved > from KSEG3 to > KSEG0. I think there's still some things wrong with > some of these > routines. I'll send what I have, if I have something > better, in a > few. I think this is an excellent start. > > : best > : Neel > : > : ==== > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 > - > /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c > ==== > : 93a94 > : > ASSYM(PAGE_SHIFT, PAGE_SHIFT); > : ==== > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 > - > /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S > ==== > : 84d83 > : < #define PAGE_SHIFT 34 > > Can you resend as a unified diff? > > Warner > > > : 91d89 > : < #define PAGE_SHIFT 2 > : 235d232 > : < li v0, > MIPS_KSEG3_START + 0x0fff0000 # invalid address > : 238d234 > : < _MTC0 v0, > COP_0_TLB_HI # Mark > entry high as invalid > : 241a238,247 > : > > : > # > : > # Load invalid entry, each TLB > entry should have it's own bogus > : > # address calculated by following > expression: > : > # MIPS_KSEG0_START + 2 * i * > PAGE_SIZE; > : > # One bogus value for every TLB > entry might cause MCHECK exception > : > # > : > sll t3, t1, > PAGE_SHIFT + 1 > : > li v0, > MIPS_KSEG0_START # > invalid address > : > addu v0, t3 > : 248c254 > : < _MTC0 t0, > COP_0_TLB_HI # Restore > the PID > : --- > : > _MTC0 v0, > COP_0_TLB_HI # Mark > entry high as invalid > : 250c256 > : < addu t0, t0, 8 > * 1024 > : --- > : > addu v0, v0, 8 > * 1024 > : 292c298 > : < li t1, > MIPS_KSEG0_START + 0x0fff0000 > : --- > : > li t1, > MIPS_KSEG0_START > : 297c303 > : < # MIPS_KSEG0_START + 0x0fff0000 + > 2 * i * PAGE_SIZE; > : --- > : > # MIPS_KSEG0_START + 2 * i * > PAGE_SIZE; > : 476c482,492 > : < li v0, > MIPS_KSEG0_START + 0x0fff0000 # invalid > address > : --- > : > > : > # > : > # Load invalid entry, each TLB > entry should have it's own bogus > : > # address calculated by following > expression: > : > # MIPS_KSEG0_START + 2 * i * > PAGE_SIZE; > : > # One bogus value for every TLB > entry might cause MCHECK exception > : > # > : > sll t3, t1, > PAGE_SHIFT + 1 > : > li v0, > MIPS_KSEG0_START # > invalid address > : > addu v0, t3 > : > > : ==== > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/swtch.S#1 > - > /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/swtch.S > ==== > : 84d83 > : < #define PAGE_SHIFT 34 > : 91d89 > : < #define PAGE_SHIFT 2 > : 364c362 > : < li t1, > MIPS_KSEG0_START + 0x0fff0000 # invalidate > tlb entry > : --- > : > li t1, > MIPS_KSEG0_START # > invalidate tlb entry > : > : > : --- On Wed, 7/1/09, M. Warner Losh > wrote: > : > : > From: M. Warner Losh > : > Subject: Re: Machine Check exception during bootup > : > To: neelnatu@yahoo.com > : > Cc: freebsd-mips@freebsd.org > : > Date: Wednesday, July 1, 2009, 7:39 AM > : > In message: <14584.70267.qm@web34403.mail.mud.yahoo.com> > : > > Neelkanth Natu > : > > : > writes: > : > : > : > > r02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S > : > ==== > : > : @@ -81,14 +81,14 @@ > : > : #define > _MFC0 > : > dmfc0 > : > : #define > _MTC0 > : > dmtc0 > : > : #define WIRED_SHIFT 34 > : > : -#define PAGE_SHIFT 34 > : > : +#define PAGE_SHIFT 12 > : > : #else > : > : #define _SLL sll > : > : #define _SRL > : > srl > : > : #define > _MFC0 > : > mfc0 > : > : #define > _MTC0 > : > mtc0 > : > : #define WIRED_SHIFT 2 > : > : -#define PAGE_SHIFT 2 > : > : +#define PAGE_SHIFT 12 > : > : #endif > : > > : > These are wrong. PAGE_SHIFT is supposed to be > the bit > : > position in the > : > TLB, not the size of the page for > multiplication. At > : > least in thoery, > : > but looking at the manual doesn't even bear that > out... > : > > : > However, it appears it isn't used that way at all in > the > : > rest of the > : > code. This means we should move it outside of > the > : > #ifdef, since it > : > has nothing to do with ISA we're compiling for. > : > > : > : .set > : > noreorder > : > # Noreorder is default > style! > : > : #if defined(ISA_MIPS32) > : > : @@ -232,22 +232,30 @@ > : > : mtc0 zero, > : > COP_0_STATUS_REG # > : > Disable interrupts > : > : ITLBNOPFIX > : > : mfc0 t1, > : > COP_0_TLB_WIRED > : > : - li v0, > : > MIPS_KSEG3_START + 0x0fff0000 # invalid address > : > : _MFC0 t0, > : > COP_0_TLB_HI # Save the > : > PID > : > : > : > : - _MTC0 v0, > : > COP_0_TLB_HI # Mark > : > entry high as invalid > : > : _MTC0 zero, > : > COP_0_TLB_LO0 # Zero > : > out low entry0. > : > : _MTC0 zero, > : > COP_0_TLB_LO1 # Zero > : > out low entry1. > : > : mtc0 zero, > : > COP_0_TLB_PG_MASK # Zero out > mask entry. > : > : + > : > : + # > : > : + # Load invalid entry, each TLB > entry > : > should have it's own bogus > : > : + # address calculated by following > : > expression: > : > : + # MIPS_KSEG0_START + 0x0fff0000 + 2 > * > : > i * PAGE_SIZE; > : > : + # One bogus value for every TLB > entry > : > might cause MCHECK exception > : > : + # > : > : + sll t3, t1, > : > PAGE_SHIFT + 1 > : > : + li v0, > : > MIPS_KSEG0_START + 0x0fff0000 # > invalid > : > address > : > : + addu v0, t3 > : > > : > I'll note that NetBSD doesn't add the 0x0fff0000 on > the end > : > here. I > : > don't understand why we do it, even though I likely > added > : > this to the > : > port. Does it work without it? > : > > : > Warner > : > > : > : > : > : > : >