From owner-svn-src-all@freebsd.org Wed Oct 30 01:41:15 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 8E87D173740; Wed, 30 Oct 2019 01:41:15 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 472rlH37xXz4HGj; Wed, 30 Oct 2019 01:41:15 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4F55E2D58; Wed, 30 Oct 2019 01:41:15 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x9U1fF7D005429; Wed, 30 Oct 2019 01:41:15 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x9U1fEPA005427; Wed, 30 Oct 2019 01:41:14 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201910300141.x9U1fEPA005427@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: Conrad Meyer Date: Wed, 30 Oct 2019 01:41:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r354162 - in head/sys/x86: include x86 X-SVN-Group: head X-SVN-Commit-Author: cem X-SVN-Commit-Paths: in head/sys/x86: include x86 X-SVN-Commit-Revision: 354162 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Oct 2019 01:41:15 -0000 Author: cem Date: Wed Oct 30 01:41:14 2019 New Revision: 354162 URL: https://svnweb.freebsd.org/changeset/base/354162 Log: amd64: Define and decode new AMD64 feature bits These are documented in revisions 3.32 of the public AMD64 Vol. 2 and revision 3.28 of Vol. 3, published October and September 2019, respectively. Modified: head/sys/x86/include/specialreg.h head/sys/x86/x86/identcpu.c Modified: head/sys/x86/include/specialreg.h ============================================================================== --- head/sys/x86/include/specialreg.h Wed Oct 30 01:35:00 2019 (r354161) +++ head/sys/x86/include/specialreg.h Wed Oct 30 01:41:14 2019 (r354162) @@ -71,6 +71,7 @@ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ +#define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */ #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ #define CR4_PCIDE 0x00020000 /* Enable Context ID */ @@ -90,6 +91,7 @@ #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ #define EFER_TCE 0x000008000 /* Translation Cache Extension */ +#define EFER_MCOMMIT 0x00020000 /* Enable MCOMMIT (AMD) */ /* * Intel Extended Features registers @@ -384,6 +386,9 @@ #define AMDFEID_CLZERO 0x00000001 #define AMDFEID_IRPERF 0x00000002 #define AMDFEID_XSAVEERPTR 0x00000004 +#define AMDFEID_RDPRU 0x00000004 +#define AMDFEID_MCOMMIT 0x00000100 +#define AMDFEID_WBNOINVD 0x00000200 #define AMDFEID_IBPB 0x00001000 #define AMDFEID_IBRS 0x00004000 #define AMDFEID_STIBP 0x00008000 Modified: head/sys/x86/x86/identcpu.c ============================================================================== --- head/sys/x86/x86/identcpu.c Wed Oct 30 01:35:00 2019 (r354161) +++ head/sys/x86/x86/identcpu.c Wed Oct 30 01:41:14 2019 (r354162) @@ -1067,6 +1067,9 @@ printcpuinfo(void) "\001CLZERO" "\002IRPerf" "\003XSaveErPtr" + "\005RDPRU" + "\011MCOMMIT" + "\012WBNOINVD" "\015IBPB" "\017IBRS" "\020STIBP" @@ -2355,7 +2358,7 @@ print_svm_info(void) "\017" "\020V_VMSAVE_VMLOAD" "\021vGIF" - "\022" + "\022GMET" /* Guest Mode Execute Trap */ "\023" "\024" "\025"