From owner-cvs-src-old@FreeBSD.ORG Wed Jan 12 13:16:49 2011 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C85B11065741 for ; Wed, 12 Jan 2011 13:16:49 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id B64808FC12 for ; Wed, 12 Jan 2011 13:16:49 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.4/8.14.4) with ESMTP id p0CDGngE065875 for ; Wed, 12 Jan 2011 13:16:49 GMT (envelope-from jchandra@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.4/8.14.4/Submit) id p0CDGnnT065874 for cvs-src-old@freebsd.org; Wed, 12 Jan 2011 13:16:49 GMT (envelope-from jchandra@repoman.freebsd.org) Message-Id: <201101121316.p0CDGnnT065874@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to jchandra@repoman.freebsd.org using -f From: "Jayachandran C." Date: Wed, 12 Jan 2011 13:16:35 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/mips/rmi xlr_machdep.c X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Jan 2011 13:16:49 -0000 jchandra 2011-01-12 13:16:35 UTC FreeBSD src repository Modified files: sys/mips/rmi xlr_machdep.c Log: SVN rev 217304 on 2011-01-12 13:16:35Z by jchandra The message ring interrupt needs to be enabled for all cpus, not just the ones which run the message ring handler. Some bits of the interrupt mask are part of the status register which is saved with the process context, and these bits are initialized from the cpu on which the process is created. This means that all the processes should have the same value for these interrupt mask bits, so that the interrupt mask remains the same regardless of what thread is scheduled on the cpu. Submitted by: Sriram Gorti (srgorti at netlogicmicro dot com) Revision Changes Path 1.27 +52 -65 src/sys/mips/rmi/xlr_machdep.c